TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 766

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

6.2
a. AM0 and AM1 pins
b. Reserved address areas
c. Standby mode (IDLE1)
d. Warm-up timer
e. Watchdog timer
f. AD converter
g. CPU (Micro DMA)
h. Undefined SFR
i. POP SR instruction
Notes
These pins are connected to the V
alter the level when the pin is active.
The 16 bytes area (FFFFF0H ∼ FFFFFFH) cannot be used since it is reserved for use as
internal area. If using an emulator, an optional 64 Kbytes of the 16M bytes area is used for
emulator control. Therefore, if using an emulator, this area cannot be used.
When the HALT instruction is executed in IDLE1 mode (in which only the oscillator operates),
RTC (Real-time-clock) and MLD (Melody-alarm-generator) operate. When necessary, stop the
circuit before the HALT instruction is executed.
The warm-up timer operates when STOP mode is released, even if the system is using an
external oscillator. As a result, a time equivalent to the warm-up time elapses between input
of the release request and output of the system clock.
The watchdog timer starts operation immediately after a reset is released. Disable the
watchdog timer when it is not to be used.
The string resistor between the VREFH and VREFL pins can be cut by program so as to
reduce power consumption. When STOP mode is used, disable the resistor using the program
before the HALT instruction is executed.
Only the “LDC cr, r” and “LDC r, cr” instructions can be used to access the control registers in
the CPU (e.g., the transfer source address register (DMASn).).
The value of an undefined bit in an SFR is undefined when read.
Please execute the POP SR instruction during DI condition.
CC
92CF26A-764
(Power supply level) or the V
SS
(Grand level) pin. Do not
TMP92CF26A
2009-06-25