TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 85

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
INTCLR
(3) Interrupt request flag clear register
(4) Micro DMA start vector registers
Interrupt
clear control
vector, as given in Table 3.5.1 to the register INTCLR.
execution of the DI instruction.
DMA. The interrupt source whose micro DMA /HDMA start vector value matches the vector set
in one of these registers is designated as the micro DMA /HDMA start source.
value reaches “0”, the micro DMA /HDMA transfer end interrupt corresponding to the channel
is sent to the interrupt controller, the micro DMA /HDMA start vector register is cleared, and
the micro DMA /HDMA start source for the channel is cleared. Therefore, in order for micro
DMA /HDMA processing to continue, the micro DMA /HDMA start vector register must be set
again during processing of the micro DMA /HDMA transfer end interrupt.
channel, the lowest numbered channel takes priority.
different channels, the interrupt generated on the lower-numbered channel is executed until
micro DMA /HDMA transfer is complete. If the micro DMA /HDMA start vector for this channel
has not been set in the channel’s micro DMA /HDMA start vector register again, micro DMA
/HDMA transfer for the higher-numbered channel will be commenced. (This process is known as
micro DMA /HDMA chaining.)
Name
The interrupt request flag is cleared by writing the appropriate micro DMA /HDMA start
For example, to clear the interrupt flag INT0, perform the following register operation after
These registers assign micro DMA /HDMA processing to sets which source corresponds to
When the micro DMA transfer counter (DMACn) or HDMA transfer counter B (HDMACBn)
If the same vector is set in the micro DMA /HDMA start vector registers of more than one
Accordingly, if the same vector is set in the micro DMA /HDMA start vector registers for two
Address
(Prohibit
RMW)
F8H
INTCLR
CLRV7
7
0
←
0AH
CLRV6
92CF26A-83
6
0
CLRV5
5
0
; Clears interrupt request flag INT0.
CLRV4
Interrupt vector
4
0
W
CLRV3
3
0
CLRV2
2
0
TMP92CF26A
CLRV1
2009-06-25
1
0
CLRV0
0
0