TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 9

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

D0 to D7
P10 to P17
D8 to D15
P40 to P47
A0 to A7
P50 to P57
A8 to A15
P60 to P67
A16 to A23
P70
P71
P72
P73
EA24
P74
EA25
P75
R/
NDR/ B
P76
P80
P81
P82
P83
P84
P85
RD
NDRE
NDWE
CS
CS
SDCS
CS
CSZA
SDCS
CS
CSXA
CSZB
CSZC
WRLL
WRLU
WAIT
Pin name
2.2
W
1
0
2
3
The names of the input/output pins and their functions are described below.
Pin names and Functions
Number
of Pins
8
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 2.2.1 Pin names and functions (1/6)
Data: Data bus D0 to D7
Port 1: I/O port input or output specifiable in units of bits
Data: Data bus D8 to D15
Port 4: Output port
Address: Address bus A0 to A7
Port 5: Output port
Address: Address bus A8 to A15
Port 6: I/O port input or output specifiable in units of bits
Address: Address bus A16 to A23
Port 70: Output port
Read: Outputs strobe signal to read external memory
Port 71: Output port
Write: Outputs strobe signal for writing data on pins D0 to D7
NAND Flash read: Outputs strobe signal to read external NAND-Flash
Port 72: I/O port
Write: Outputs strobe signal for writing data on pins D8 to D15
NAND Flash write: Write enable for NAND Flash
Port 73: I/O port
Expanded address 24
Port 74: I/O port
Expanded address 25
Port 75: I/O port
Read/Write: “High” represents read or dummy cycle; “Low” represents write cycle
NAND Flash Ready(1) / Busy(0) input
Port 76: I/O port
Wait: Signal used to request CPU bus wait
Port 80: Output port
Chip select 0: Outputs “Low” when address is within specified address area
Port 81: Output port
Chip select 1: Outputs “Low” when address is within specified address area
Chip select for SDRAM: Outputs “Low” when the address is within SDRAM address area
Port 82: Output port
Chip select 2: Outputs “Low” when address is within specified address area
Expanded address ZA: Outputs “Low” when address is within specified address area
Chip select for SDRAM: Outputs “Low” when the address is within SDRAM address area
Port 83: Output port
Chip select 3: Outputs “Low” when address is within specified address area
Expanded address XA: Outputs “Low” when address is within specified address area
Port 84: Output port
Expanded address ZB: Outputs “Low” when address is within specified address area
Port 85: Output port
Expanded address ZC: Outputs “Low” when address is within specified address area
92CF26A-7
Functions
TMP92CF26A
2009-06-25