TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 93

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

HDMACAn
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note: Read-modify-write instructions can be used on all these registers.
(3) HDMACAn (DMA Transfer Count A Setting Register)
performed by one DMA request. HDMACAn contains 16 bits and can specify up to
65536 transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536
transfers). Even when the transfer count A is updated by DMA execution, HDMACAn
is not updated.
The HDMACAn register is used to set the number of times a DMA transfer is to be
HDMACA0 to HDMACA5 have the same configuration.
DnCA15
DnCA7
Transfer count A
15
7
0
0
(0909H)
(0919H)
(0929H)
(0939H)
(0949H)
(0959H)
[15:8]
DnCA14
DnCA6
14
6
0
0
Figure3.6.4 HDMACAn Register
DnCA13
DnCA5
HDMACAn Register
13
5
0
0
Transfer count A
92CF26A-91
Transfer count A [15:8] for DMAn
Transfer count A [7:0] for DMAn
HDMACA0
HDMACA1
HDMACA2
HDMACA3
HDMACA4
HDMACA5
(0908H)
(0918H)
(0928H)
(0938H)
(0948H)
(0958H)
[7:0]
DnCA12
DnCA4
12
4
0
0
R/W
R/W
DnCA11
DnCA3
11
3
0
0
DnCA10
DnCA2
10
2
0
0
DnCA1
DnCA9
1
9
0
0
TMP92CF26A
DnCA0
DnCA8
2009-06-25
0
8
0
0