TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 94

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
HDMACBn
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note: Read-modify-write instructions can be used on all these registers.
(4) HDMACBn (DMA Transfer Count B Setting Register)
made. HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one
request, FFFFH = 65535 requests, 0000H = 65536 requests). When the transfer count
B is updated by DMA execution, HDMACBn is also updated.
The HDMACBn register is used to set the number of times a DMA request is to be
HDMACB0 to HDMACB5 have the same configuration.
DnCB15
DnCB7
Transfer count B
15
7
0
0
(090BH)
(091BH)
(092BH)
(093BH)
(094BH)
(095BH)
[15:8]
DnCB14
DnCB6
14
6
0
0
Figure3.6.5 HDMACBn Register
DnCB13
DnCB5
HDMACBn Register
13
5
0
0
Transfer count B
92CF26A-92
Transfer count B [15:8] for DMAn
Transfer count B [7:0] for DMAn
HDMACB0
HDMACB1
HDMACB2
HDMACB3
HDMACB4
HDMACB5
(090AH)
(091AH)
(092AH)
(093AH)
(094AH)
(095AH)
[7:0]
DnCB12
DnCB4
12
4
0
0
R/W
R/W
DnCB11
DnCB3
11
3
0
0
DnCB10
DnCB2
10
2
0
0
DnCB1
DnCB9
1
9
0
0
TMP92CF26A
DnCB0
DnCB8
2009-06-25
0
8
0
0

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