TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 96

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

HDMATR
(097FH)
HDMAE
(097EH)
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Note: In case of using S/W start with HDMA, transmission start is to set to “1” DMAR register. However DMAR
Note: Read-modify-write instructions can be used on this register.
(6) HDMAE (DMA Operation Enable Register)
(7) HDMATR (DMA Maximum Bus Occupancy Time Setting Register)
Note: Read-modify-write instructions can be used on this register.
register can't be used to confirm flag of transmission end. DMAR register reset to "0" when HDMA release bus
occupation once with HDMATR function.
occupy the bus. The TMP92CF26A does not have priority levels for bus arbitration.
Therefore, once the DMAC owns the bus, other masters (such as the LCDC) must wait
until the DMAC completes its transfer operation and releases the bus. This could lead
to problems in the system. For example, if the LCDC cannot own the bus as required,
the LCD display function may not work properly. To avoid such a situation, the DMAC
limits the duration of its bus occupancy by using this timer register. When the DMAC
occupies the bus for the duration of time set in this register, it releases the bus even if
the specified DMA operation has not been completed yet. After waiting for 16 states,
the DMAC asserts a bus request again to execute the rest of the DMA operation.
the bus. To set the maximum bus occupancy time, ensure that the HDMAE register is
set to “00H” and set HDMATR<DMATE> to “1” and <DMATR6:0> to the desired value.
Timer
operation
0: Disable
1: Enable
The HDMAE register is used to enable or disable the DMAC operation.
Bits 0 to 5 correspond to channels 0 to 5. Unused channels should be set to “0”.
The HDMATR register is used to set the maximum duration of time the DMAC can
The DMAC counts the bus occupancy time regardless of which channel is occupying
DMATE
7
7
0
DMATR6
6
6
0
Figure3.6.8 HDMATR Register
Figure3.6.7 HDMAE Register
DMATR5
DMAE5
The value to be set in <DMATR6:0> should be obtained by
HDMATR Register
HDMAE Register
5
0
5
0
92CF26A-94
“maximum bus occupancy time / (256/f
Maximum bus occupancy time setting
DMATR4
DMAE4
4
4
0
0
“00H” cannot be set.
R/W
DMA channel operation
DMATR3
DMAE3
3
3
0
0
0: Disable
1: Enable
R/W
DMATR2
DMAE2
2
2
0
0
SYS
DMATR1
)”.
DMAE1
1
0
1
0
TMP92CF26A
DMATR0
DMAE0
2009-06-25
0
0
0
0