TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 98

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SDCLK
int_xx
busrq
busak
A23 ∼ A0
D15 ∼ D0
CS
RD
SRWR
SRLUB
CS
SRLLB
1
2
Source address
Destination address
(3) Transfer source and destination memory setting
(2) Bus arbitration
(4) Operation timing
Table 3.6.1 Difference point of address setting between HDMA and micro DMA
SDRAM controller) that function as bus masters apart from the CPU. These controllers
operate independently and assert a bus request as required. The controller that
receives a bus acknowledgement acts as the bus master. No priorities are assigned to
these three controllers, and bus requests are processed in the order in which they are
asserted. Once one of the controllers owns the bus, bus requests from other controllers
are put on hold until the bus is released again. While one of the controllers is occupying
the bus, CPU processing including non-maskable interrupt requests is also put on hold.
or I/O to be accessed by the DMAC. Even when the MMU is used in external memory,
the addresses to be accessed by the DMAC should be specified using logical addresses.
The DMAC accesses the specified source and destination addresses according to the
bus width and number of waits set in the memory controller and the bank settings
made in the MMU.
supported. Therefore, specify an even-numbered address for transferring 2 bytes and
an address that is an integral multiple of 4 for transferring 4 bytes.
from 16-bit memory connected with the
CS
CPU execution cycle
1
The TMP92CF26A includes three controllers (DMA controller, LCD controller,
Either internal or external memory can be set as the source and destination memory
Although the bus sizing function is supported, the address alignment function is not
The following diagram shows an example of operation timing for transferring 2 bytes
Undefined after interrupt
request is asserted until
DMAC read cycle is
started
area.
Data Length
1byte
2byte
4byte
1byte
2byte
4byte
92CF26A-96
DMAC/read
800000H
1234H
Address in multiples of 4
Address in multiples of 4
CS
Even address
No restriction
Even address
No restriction
2
HDMA
area to 8-bit memory connected with the
400000H
ZZ34H
DMAC/write
400001H
ZZ12H
Micro DMA
No restriction
TMP92CF26A
2009-06-25
CPU execution
cycle