FSAR001B Fairchild Semiconductor, FSAR001B Datasheet - Page 8

• Manufacturer Part Number: FSAR001B
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FSAR001 • Rev. 1.0.0
Functional Description
The FSAR001 is a compact, inductor-free, and highly
monolithic AC/DC linear converter housed in 8-lead DIP
packages and designed for non-isolated AC/DC
converter
provides universal AC voltage input from 80V
265V
for the non-isolated AC/DC converter operating safety
and stability. The FSAR001 integrates many protection
functions, including output current limiter (I
under-voltage
protector (OTP), V
AC synchronous signal detect function (V
As the FSAR001 operates in a typical application, the
startup current flows through the startup pin (V
charges V
larger than V
AC synchronous signal, the LDO is turned on and
creates output voltage (V
energy of V
operation and load power dissipation. The behavior is
shown in Figure 17 and the energy is recharged during
conduction angle interval (settled by R3 and R4) and
under OVP function limitation (V
increasing
FSAR001 sets the V
regulator. The V
below 50V
sense voltage), detailed in the following sections.
Startup Current
During FSAR001 startup, the startup current through
the rectifier and V
maximum start current of V
synchronous current controlled by R3 (1MΩ) and R4
(13kΩ), shown in Figure 1. The FSAR001 remains off
until the V
voltage is created at the same time. After the FSAR001
turns on, the V
loop. The major energy path changes from V
the inner power MOSFET MV (V
Max
RMS
V
CV
IN
and fixed-DC output voltage with current limiter
DD
DD
RMS
DD
max
and
DD
Figure 17. Operating Principle
Max
TH_ON
LDO
voltage is larger than V
Conduction angle
capacitor. When the voltage of V
capacitor decreases because of the chip
(set by R3&R4)
settled by AC synchronous signal (DET
ST
protection
V
DD
home
, the FSAR001 is turned on. After one
DD
DD(capacitance)
ST
function is disabled by the control
efficiency
DD
capacitor recovery angle controls
pin charges the V
over-voltage protection (OVP), and
OVP voltage at 8.5V for 5V LDO
I
IN
appliances.
OUT
ST
(UVP),
). At steady state, the
and
pin of 3.75mA and the
IN
DD-OVPH
LDO
).
TH-ON
system
over-temperature
DD
). With a view to
The
DET
and the output
capacitor with
LIMIT
).
ST
FSAR001
), output
Load
pin from
stability,
V
ST
OUT
RMS
) and
DD
to
is
8
OUT Pin Under-Voltage Protection
When the output power is larger than the maximum
handling power of FSAR001, the condition causes the
output voltage to drop. Until the output voltage is less
than output nominal voltage -12% (5V – 0.625V =
4.375V), the UVP function disables the LDO stage and
waits until the next AC synchronous signal to restart the
FSAR001 automatically.
Current Limit
The FSAR001 includes a current limiter (ILIMIT) for safe
LDO operation. The limiter monitors the loading current
and directly controls the output delivery current of LDO.
The typical limited current set is 140mA to avoid the
output shorted to ground for an indefinite amount of
time without damaging the part. At over-current
operation, the I
current and causes the unregulated output voltage to
drop until the UVP function occurs.
Over-Temperature Protection
The FSAR001 operates in highly converting ratio. The
thermal energy of FSAR001 is generated by the inner
converting power of the MOSFET. When the junction
temperature (T
disables LDO stage and waits for the next AC
synchronous signal to restart. The over-temperature
hysteresis range is 40°C. After startup, the OTP
function monitors the junction temperature. When
junction temperature decreases to the (T
OTP function enables the signal and allows LDO turn
on. If not, OTP function keeps the output function
disabled
temperature. The OTP function is designed to protect
against abnormal conditions and over-power operation.
DET Pin Selection
The DET pin connects to the commutated AC bus. It
sinks commutated AC voltage waveform used to
provide the AC synchronous signal and to set the V
capacitor recovery conduction angle. For synchronous
signal function, the AC synchronous signal used to
enable output voltage of the LDO and to trigger the
output stage protection with UVP and OTP. To limit the
recovery-conduction angle of the V
DET pin sense voltage (V
~0.95V. During the sense-voltage range of the DET pin,
the V
MOSFET until the OVP function is operating in every
synchronous cycle. As shown in Figure 18, the DET pin
sense voltage limits the charge time of t0~t1 and t2~ts/2
settled by R3 and R4. The maximum commutated input
voltage of FSAR001 can be determined by the following
equation with the maximum DET sense voltage defined:
DD
capacitor can be charged by the power
and continuously monitors the junction
LIMIT
J
) exceeds 150°C, the OTP function
function limits the maximum output
DET
) is set between 0.14V
DD
capacitor, the
OTP-THYS
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), the
DD