SG5842JA Fairchild Semiconductor, SG5842JA Datasheet - Page 10

• Manufacturer Part Number: SG5842JA
• Description: The highly integrated SG5842A/JA series of PWM controllers provides several features to enhance the performance of flyback converters
• Manufacturer: Fairchild Semiconductor

© 2007 Fairchild Semiconductor Corporation
SG5842A/SG582JA • Rev. 1.4.3
Functional Description
Startup Current
The typical startup current is only 14µA, which allows a
high-resistance, low-wattage startup resistor to be used to
minimize power loss. A 1.5MΩ/0.25W startup resistor and
a 10µF/25V V
AC/DC adapter with a universal input range.
Operating Current
The required operating current has been reduced to
4mA. This results in higher efficiency and reduces the
V
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation
frequency under light-load conditions. To avoid acoustic
noise problems, the minimum PWM frequency is set
above 22KHz. This green-mode function dramatically
reduces power consumption under light-load and zero-
load conditions. Power supplies using this controller can
meet even the strictest international standby power
regulations.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the controller.
This current is used to determine the center PWM
frequency. Increasing the resistance reduces PWM
frequency. Using a 26KΩ resistor, R
corresponding 65KHz PWM frequency. The relationship
between R
The range of the PWM oscillation frequency is designed
as 47KHz ~ 109KHz.
SG5842JA also integrates a frequency hopping function
internally. The frequency variation ranges from around
62KHz to 68KHz for a center frequency of 65KHz. The
frequency hopping function helps reduce EMI emission
of a power supply with minimum line filters.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate drive.
DD
f
PWM
hold-up capacitance requirement.
=
R
I
1690
I
and the switching frequency is:
(K
to
DD
Ω
)
hold-up capacitor are sufficient for an
(KHz)
continuously
decrease
I
, results in a
the
PWM
(1)
10
Under-Voltage Lockout (UVLO)
The turn-on/turn-off thresholds are fixed internally at
16.5V/10.5V. To enable a SG5842A/JA controller during
startup, the hold-up capacitor must first be charged to
16.5V through the startup resistor.
The hold-up capacitor continues to supply V
energy can be delivered from the auxiliary winding of
the main transformer. V
during this startup process. This UVLO hysteresis
window ensures that the hold-up capacitor can
adequately supply V
Gate Output / Soft Driving
The SG5842A/JA BiCMOS output stage is a fast totem-
pole gate driver. Cross-conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 18V Zener diode to protect the power MOSFET
transistors from harmful over-voltage gate signals. A
soft-driving waveform is implemented to minimize EMI.
Slope Compensation
The sensed voltage across the current sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. The built-in slope compensation
function improves power supply stability and prevents
peak-current-mode control from causing sub-harmonic
oscillations.
SG5842A/JA controller produces a positively sloped,
synchronized ramp signal.
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
R
output GATE drive is turned off after a small delay, t
This delay introduces additional current proportional to
t
the input voltage V
larger additional current and the output power limit is
higher than under low input line voltage. To compensate
this variation for a wide AC input range, a sawtooth
power-limiter (saw limiter) is designed to solve the
unequal power-limit problem. The saw limiter is
designed as a positive ramp signal (V
the inverting input of the OCP comparator. This results
in a lower current limit at high-line inputs than at low-
line inputs.
V
V
damage due to abnormal conditions. Once the V
voltage is over the V
(V
off. The PWM pulses stay latched off until the power
supply is unplugged from the mains outlet.
PD
DD
S
DD
DD-OVP
, reaches the threshold voltage, around 0.85V; the
• V
Over-Voltage Protection (OVP)
over-voltage protection is built in to prevent
IN
) and lasts for t
/ L
P
. The delay is nearly constant regardless of
Within
IN.
DD
DD
Higher input voltage results in a
during startup.
D-OVP
every
DD
over-voltage protection voltage
must not drop below 10.5V
, the PWM pulse is latched
switching
LIMIT_RAMP
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cycle,
DD
) fed to
before
the
PD
DD
.