SG6859A Fairchild Semiconductor, SG6859A Datasheet - Page 9

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SG6859A

Manufacturer Part Number
SG6859A
Description
This highly integrated PWM controller provides several special enhancements designed to meet the low standby-power needs of low-power SMPS
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2007 Fairchild Semiconductor Corporation
SG6859A • Rev. 1.0.4
Operation Description
SG6859A devices integrate many useful designs into
one controller for low-power, switch-mode power
supplies. The following descriptions highlight some of
the features of the SG6859A series.
Startup Current
The startup current is only 9μA. Low startup current
allows a startup resistor with high resistance and low-
wattage to supply the startup power for the controller. A
1.5MΩ, 0.25W, startup resistor and a 10µF/25V V
hold-up capacitor are sufficient for an AC-to-DC power
adapter with a wide input range (100V
Operating Current
The operating current has been reduced to 3mA. The
low operating current results in higher efficiency and
reduces the V
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load conditions. On-time is limited to provide
stronger protection against brownouts and other
abnormal conditions. The feedback current, which is
sampled from the voltage feedback loop, is taken as the
reference. Once the feedback current exceeds the
threshold current, the switching frequency starts to
decrease.
reduces power consumption under light-load and zero-
load conditions. Power supplies using the SG6859A
can meet even the strictest regulations regarding
standby power consumption.
Oscillator Operation
A resistor connected from the RI pin to ground
generates a constant current source used to charge an
internal capacitor. The charge time determines the
internal clock speed and the switching frequency.
Increasing the resistance reduces the amplitude of the
input current and the switching frequency. A 95kΩ R
resistor results in a 50µA constant current, I
70kHz switching frequency. The relationship between R
and the switching frequency is:
The recommended f
Leading-Edge Blanking
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense-resistor. To avoid premature
termination of the switching pulse, a 320ns leading-
edge blanking time is built in. Conventional RC filtering
can be omitted. During this blanking period, the current-
limit comparator is disabled and cannot switch off the
gate driver.
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
R
f
PWM
S
, reaches the threshold voltage (around 1V), the
=
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(k
Ω
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DD
(kHz)
hold-up capacitance requirement.
green-mode
PWM
is from 50kHz to 80kHz.
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output GATE drive is turned off following a short
propagation
introduces
t
regardless of the input line voltage V
voltages result in larger additional currents. At high
input line voltages, the output power limit is higher than
at low input line voltages. To compensate for this output
power limit variation across a wide AC input range, the
threshold voltage is adjusted by adding a positive ramp.
This ramp signal rises from 0.8V to 1V, then flattens out
at 1V. A smaller threshold voltage forces the output
GATE drive to terminate earlier, which reduces the total
PWM turn-on time and makes the output power equal to
that of low line input. This proprietary internal
compensation ensures a constant output power limit for
a wide AC input voltage range (90V
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 9.5V. During startup, the hold-up capacitor
must be charged to 16.5V through the startup resistor to
enable the SG6859A. The hold-up capacitor continues
to supply VDD until power can be delivered from the
auxiliary winding of the main transformer. V
drop below 9.5V during this startup process. This UVLO
hysteresis window ensures that hold-up capacitor is
adequate to supply V
Gate Output
The BiCMOS output stage is a fast totem pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
17V Zener diode to protect power MOSFET transistors
against undesired over-voltage gate signals.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current mode control. The SG6859A has a
synchronized, positively-sloped ramp built-in at each
switching cycle. The slope of the ramp is:
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
continuous-conduction
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the SG6859A, and increasing
power MOS gate resistance improve performance.
PD•
0.36 ×
Duty(max.)
V
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Duty
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. The propagation delay is nearly constant,
an
delay,
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PD
during startup.
mode
.
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AC
propagation
IN
to 264V
. Higher input line
proportional
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