FAN103 Fairchild Semiconductor, FAN103 Datasheet
FAN103
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FAN103 Summary of contents
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... PWM frequency under light-load conditions. This green mode assists the power supply in meeting the power conservation requirement. By using the FAN103, a charger can be implemented with few external components and minimized cost. A typical output CV/CC characteristic envelope is shown in Figure 1. Figure 1. Typical Output V-I Characteristic ...
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... Application Diagram Input Internal Block Diagram © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0 sn2 sn1 VDD VDD VS GATE 7 N.C GATE GND ...
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... Ground Connect 8 HV High Voltage. This pin connects to bulk capacitor for high-voltage startup. © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 F: Fairchild Logo Z: Plant Code X: 1-Digit Year Code Y: 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (M=SOP) P: Y=Green Package M: Manufacture Flow Code Figure 4 ...
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... Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol T Operating Ambient Temperature A © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 Parameter (1)(2) <50°C) A Human Body Model, JEDEC-JESD22_A114 Charged Device Model, JEDEC-ESD22_C101 ...
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... Current-Sense Section t Propagation Delay to GATE Output PD t Minimum On Time at No-Load MIN-N V Threshold Voltage for Current Limit TH Threshold Voltage on VS Pin Smaller than V TL 0.5V © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 =15V and T =25°C. A Condition V =100V DC HV=500V, V +1V OFF Deviation V =10~25V DD ...
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... Over-Temperature-Protection Section T Threshold Temperature for OTP OTP Note: 4. When the over-temperature protection is activated, the power system enters auto restart mode and output is disabled. © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 (Continued) =15V and T =25°C. A Condition V =20V, Gate Sinks 10mA DD ...
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... Temperature (ºC) Figure 8. Operating Current (I 2.525 2.515 2.505 2.495 2.485 2.475 -40 -30 - Temperature (ºC) Figure 10. Reference Voltage (V © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 5.5 5.3 5.1 4.9 4.7 4 100 125 -40 ) Figure 7. DD- - 100 125 ) vs ...
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... Temperature (ºC) Figure 14. Supply Current Drawn from Pin HV (I vs. Temperature 2.7 2.62 2.54 2.46 2.38 2.3 -40 -30 - Temperature (ºC) Figure 16. Green Mode Starting Voltage on EA_V (V © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0 100 125 -40 Figure 13. Minimum Frequency at CCM (f 1100 1050 1000 ...
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... Typical Performance Characteristics Figure 19. Output Clamp Voltage (V Figure 20. Variation Test Voltage on COMR Pin for Cable Compensation (V © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 12 11.2 10.4 9.6 8.8 8 -40 -30 - Temperature (ºC) Figure 18. IC Bias Current (I ) vs. Temperature tc 1.6 1.5 1.4 1.3 1.2 1.1 1 -40 -30 - Temperature (ºC) ...
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... Therefore, during constant voltage regulation mode, V duty cycle while V is saturated to HIGH. During COMI constant current regulation mode, V duty cycle while V is saturated to HIGH. COMV © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 discontinuous ), input voltage ( Then, m ...
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... CV mode. As load increases, the voltage drop across the cable is compensated by increasing the reference voltage of voltage regulation error amplifier. Operating Current The operating current in FAN103 is as small as 3.2mA. The small operating current results in higher efficiency and reduces the V hold-up capacitance requirement. ...
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... DD gate driver. Gate Output The FAN103 output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 15V Zener diode to protect power MOSFET transistors against undesired over-voltage gate signals ...
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... Low standby (Pin <30mW at No Load Condition) Tight output regulation (CV: ±5%, CC: ±7%) 74.00% 72.00% 70.00% 68.00% 66.00% 64.00% 62.00% 0.250 0.500 Figure 27. Measured Efficiency and Output Regulation © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 Input Voltage Range 90~265V 0.750 1.000 Figure 28. Schematic of Typical Application Circuit ...
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... When W2 is winding, put 1 layer tape after wind first layer. TERMINAL W4R 7 9 Primary-Side Inductance Primary-Side Effective Leakage © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 (Continued) Figure 29. Bobbin Winding Diagram WIRE Ts 2UEW 0.23 2UEW 0.17 COPPER SHIELD 1.2 TEX-E 0.6*1 9 CORE ROUNDING TAPE Pin Specification 1－3 1.75mH ± ...
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... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 5.00 4.80 A 3.81 ...
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... Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.5 16 www.fairchildsemi.com ...