FAN6210 Fairchild Semiconductor, FAN6210 Datasheet
FAN6210
Related parts for FAN6210
FAN6210 Summary of contents
Page 1
... FAN6206. FAN6210 provides drive signal for the primary-side power switches by using an output signal from PWM controller. FAN6210 can be combined with any PWM controller that can drive a dual-forward converter. To obtain optimal timing for the SR drive signals, transformer winding voltage is also monitored. To ...
Page 2
... RDLY 4 2/ DET OVP + - 25.5V VDD 10/8V © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Figure 1. Typical Application Rising/Falling Delay 100ns 300ns Controlled Rising Delay GM Rising Delay 50ns One-shot Vibrator Rising/Falling Delay One-shot Vibrator 50ns 50ns Internal Bias Figure 2. Functional Block Diagram 2 7 SOUT ...
Page 3
... Sensing freewheel diode voltage. 6 VDD The power supply pin. 7 SOUT Gate driving to high- and low-side gate driver. 8 GND Ground. © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Fairchild Logo F: Z: Plant Code X: Year Code Y: Week Code TT: Package Type T: M=SOP P: Y: Green Package M: Manufacture Flow Code Figure 3 ...
Page 4
... The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol T Operating Ambient Temperature A © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Parameter < 50°C A Parameter 4 Min. Max. ...
Page 5
... DLY_XP V Output Voltage Maximum (Clamp Output Voltage LOW OL V Output Voltage HIGH OH t SOUT Rising Time R t SOUT Falling Time F © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Parameter OVP DD Stop XP Pulse PLS_OFF 100pF; L SOUT 100pF; L SOUT ...
Page 6
... Figure 9. High-Level Pulsewidth of XN Signal -40 -25 - Temperature℃ Figure 11. Delay Time to Trigger XN by SIN Rising or Falling Edge © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 = 25°C. A 9.00 8.75 8.50 8.25 8. 110 125 Figure 6. Turn-Off Threshold Voltage 150 140 130 ...
Page 7
... Dual-Forward Converter Figure 14. Key Waveforms of Dual-Forward Converter © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Figure 15 shows the typical application circuit of FAN6210. SIN is the gate drive output of the PWM and its key controller. SOUT is obtained from SIN by adding a are turned on and off ...
Page 8
... Gate drive for Free-wheeling SR Figure 16. Timing Diagram Under-Voltage Lockout (UVLO) The power-on and -off threshold of FAN6210 are fixed at 10V and 8V, respectively. The VDD pin can be connected with the power source of the PWM controller. V Pin Over-Voltage Protection DD V over-voltage protection prevents damage due to DD abnormal conditions ...
Page 9
... XP GND 2 XN SOUT OPWM 3 SIN VDD (From FAN480X) 4 RDLY DET 8.2k 1N4148 1N4148 1N4148 1N4148 1N4148 © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Input Voltage Range 90~264V AC FCP20N60 UF1007 10k 74:7 FR107 FCP20N60 68k UF1007 10k 10k 470 1 LPC1GATE1 2 LPC2 GND 0.15 3 ...
Page 10
... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0 1.75 4 ...
Page 11
... Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 11 www.fairchildsemi.com ...