CS4334 Cirrus Logic, Inc., CS4334 Datasheet

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... The CS4334/5/6/7/8/9 support all major audio data interface formats, and the individual devices differ only in the supported interface format. The CS4334 family is based on delta-sigma modulation, where the modulator output controls the reference volt- age input to an ultra-linear analog low-pass filter. This ...

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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS4334/5/6/7/8/9 DS248PP3 ...

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... Figure 11.CS4335 Data Format .......................................................................... 14 Figure 12.CS4336 Data Format .......................................................................... 14 Figure 13.CS4337 Data Format .......................................................................... 15 Figure 14.CS4338 Data Format .......................................................................... 15 Figure 15.CS4339 Data Format .......................................................................... 15 Figure 16.CS4334/5/6/7/8/9 Initialization and Power-Down Sequence .............. 16 Figure 17.Stopband Rejection............................................................................. 17 Figure 18.Transition Band................................................................................... 17 Figure 19.Transition Band................................................................................... 17 Figure 20.Passband Ripple................................................................................. 17 Figure 21.Stopband Rejection............................................................................. 18 Figure 22 ...

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... Measurement Bandwidth kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, SCLK = 6.144 MHz, Measurement Bandwidth kHz, unless otherwise specified. Test load (see Figure 1)) L Parameter Dynamic Performance for CS4334/5/6/7/8/9-KS Specified Temperature Range Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise ...

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... De-emphasis is not available in High-Rate Mode. 6. Refer to Figure 2. DS248PP3 (Continued) Base-rate Mode Symbol Min (Note -.01 - .5465 (Note 4) 50 tgd - - ±0.36/ kHz kHz - - kHz - Symbol V (Note 6) R (Note 6) C CS4334/5/6/7/8/9 High-Rate Mode Typ Max Min Typ - .4780 - - - - .4996 +.08 -. ±. .5770 - - - ...

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... Symbol normal operation I A power-down state I A (Note 7) normal operation power-down JA (1 kHz) PSRR 10 µF AOUTx R L Figure 1. Output Test Load CS4334/5/6/7/8/9 Min Typ Max - 104 - 0 110 - °C/Watt - out ...

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... DC Power Supply DS248PP3 (T = 25° 4.75V - 5.5V) A Symbol (Note (AGND = 0V; all voltages with respect to ground.) Symbol IND stg (AGND = 0V; all voltages with respect to ground.) Symbol VA 4.75 CS4334/5/6/7/8/9 Min Typ Max Units 2 0 ± Min Max Units -0.3 6 ± ...

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... VA = 4.75V - 5.5V; Inputs: Logic 0 = 0V, A Symbol Fs MCLK/LRCK = 512 MCLK/LRCK = 512 t sclkl t sclkh t sclkw t sclkw t slrd t slrs t sdlrs t sdh (Note 9) (Note 10) t sclkw t sclkr t sdlrs t sdh t sdh CS4334/5/6/7/8/9 Min Typ Max 2 - 100 10 - 1000 10 - 1000 21 - 1000 21 - 1000 31 - 1000 31 - 1000 ...

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... LRCK SCLK SDATA LRCK SDATA *INTERNAL SCLK * The SCLK pulses shown are internal to the CS4334/5/6/7/8/9. LRCK MCLK *INTERNAL SCLK SDATA * The SCLK pulses shown are internal to the CS4334/5/6/7/8/9. DS248PP3 t slrs t slrd t t sdlrs Figure 4. External Serial Mode Input Timing t sclkr t t sdlrs sdh Figure 5 ...

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... External Clock MCLK 10 + 0.1 µ 3.3 µF 8 AOUTL 267 k CS4334 CS4335 CS4336 CS4337 CS4338 CS4339 3.3 µF 5 AOUTR 267 k AGND 6 Figure 7. Recommended Connection Diagram CS4334/5/6/7/8/9 +5V 1 µF 560 + 560 + 560 Fs(R 560) L Left Audio Output Right Audio Output DS248PP3 ...

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... GENERAL DESCRIPTION The CS4334 family of devices offers a complete stereo digital-to-analog system including digital in- terpolation, fourth-order delta-sigma digital-to-an- alog conversion, digital de-emphasis and analog filtering, as shown in Figure 8. This architecture provides a high tolerance to clock jitter. The primary purpose of using delta-sigma modula- tion techniques is to avoid the limitations of resis- ...

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... DEM/SCLK pin is low (high) for 5 consecutive falling edges of LRCK. This function is available only in the internal serial clock mode. 4.4 Initialization and Power-Down The Initialization and Power-Down sequence flow chart is shown in Figure 16. The CS4334 family en- ters the Power-Down State upon initial power-up. CS4334/5/6/7/8/9 DS248PP3 ...

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... For best performance, decoupling capaci- tors should be located as close to the device pack- age as possible with the smallest capacitor closest. 4.7 Analog Output and Filtering The analog filter present in the CS4334 family is a switched-capacitor filter followed by a continuous . Approximately Q time low pass filter. Its response, combined with ...

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... INT SCLK = MCLK/LRCK = 384 or 192 LSB MSB - 24-Bit Data Data Valid on Rising Edge of SCLK Figure 10. CS4334 Data Format ( LSB MSB - Left Justified 24-Bit Data Data Valid on Rising Edge of SCLK Figure 11. CS4335 Data Format 7 6 ...

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... Right Justified, 18-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 36 Cycles per LRCK Period Figure 15. CS4339 Data Format CS4334/5/6/7/8/9 Right Channel External SCLK Mode Right Channel ...

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... Figure 16. CS4334/5/6/7/8/9 Initialization and Power-Down Sequence 16 CS4334/5/6/7/8/9 DS248PP3 ...

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... Overall Base-Rate Frequency Response Figure 17. Stopband Rejection Figure 19. Transition Band DS248PP3 CS4334/5/6/7/8/9 Figure 18. Transition Band 0.1 0.08 0.06 0.04 0.02 0 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) Figure 20. Passband Ripple 0.35 0.4 0.45 17 ...

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... Overall High-Rate Frequency Response Figure 21. Stopband Rejection Figure 23. Transition Band 18 CS4334/5/6/7/8/9 Figure 22. Transition Band 0.25 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (normalized to Fs) Figure 24. Passband Ripple 0.35 0.4 0.45 DS248PP3 ...

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... Figure 30. THD+N vs. Frequency (BRM) System Two Cascade. CS4334/5/6/7/8 10k 12k 14k 16k 10k 10k 12k 12k ...

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... Figure 36. THD+N vs. Frequency (HRM) System Two Cascade. CS4334/5/6/7/8 10k 10k 10k 12k 12k 12k 14k 14k ...

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... Pin Name I/O 1 SDATA I Serial Audio Data Input - two’s complement MSB-first serial data is input on this pin. The data is clocked into the CS4334/5/6/7/8/9 via internal or external SCLK, and the channel is determined by LRCK. 2 DEM/SCLK I De-Emphasis/External Serial Clock Input - used for de-emphasis filter control or exter- nal serial clock input ...

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... Gain Drift - The change in gain value with temperature. Units in ppm/ 7. REFERENCES 1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper presented at the 93rd Con- vention of the Audio Engineering Society, Oc- tober 1992. 2) CDB4334/5/6/7/8/9 Evaluation Board Datasheet 22 CS4334/5/6/7/8/9 C. ° DS248PP3 ...

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... Plastic SOIC 16 to 24-bit, left justified 8-pin Plastic SOIC 24-bit, right justified 8-pin Plastic SOIC 20-bit, right justified 8-pin Plastic SOIC 16-bit, right justified 8-pin Plastic SOIC 18-bit, right justified CS4334/5/6/7/8/9 Serial Interface Internal SCLK mode s Internal SCLK mode s 23 ...

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... DIM INCHES MIN MAX 0.053 0.069 0.004 0.010 0.013 0.020 0.007 0.010 0.189 0.197 0.150 0.157 0.040 0.060 0.228 0.244 0.016 0.050 0° 8° JEDEC # : MS-012 CS4334/5/6/7/8/9 L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.02 1.52 5.80 6.20 0.40 1.27 0° 8° DS248PP3 ...

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Notes • ...

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