EPCS4 Altera Corporation, EPCS4 Datasheet
EPCS4
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EPCS4 Summary of contents
Page 1
... Windows-based PCs as well as Sun SPARC station and HP 9000 Series 700/800 Delivered with the memory array erased (all the bits set to 1) Whenever the term “serial configuration device(s)” is used in this document, it refers to Altera EPCS1, EPCS4, EPCS16, and EPCS64 devices. Core Version a.b.c variable ® ...
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... EPCS16 EPCS64 Note to (1) You can vertically migrate from the EPCS1 to the EPCS4 device since they are offered in the same device package. Similarly, you can vertically migrate from the EPCS16 to the EPCS64 device. Table 4–2 FPGA and the configuration file size. Stratix II devices can only be used with EPCS16 or EPCS64 devices. Table 4– ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Table 4–3 FPGA and the configuration file size. Cyclone II devices can be used with all serial configuration devices. Table 4–3. Serial Configuration Device for Cyclone II Devices Cyclone II Device Notes to (1) (2) Table 4–4 FPGA and the configuration file size ...
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... DCLK Address Counter Decode Logic 4–4 Configuration Handbook, Volume 2 Serial configuration devices cannot be cascaded. shows the serial configuration device block diagram. Control Logic I/O Shift Register Data Buffer Memory Array Core Version a.b.c variable DATA ASDI Status Register Altera Corporation July 2004 ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Accessing Memory in Serial Configuration Devices You can access the unused memory locations of the serial configuration device to store or retrieve data through the Nios processor and SOPC Builder. SOPC Builder is an Altera tool for creating bus-based (especially microprocessor-based) systems in Altera devices ...
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... ASDI 4–6 Configuration Handbook, Volume 2 V (1) V ( kΩ 10 kΩ Cyclone Series FPGA CONF_DONE nSTATUS nCONFIG nCE 10 kΩ DATA0 DCLK nCSO ASDO V (1) Pin 1 CC Core Version a.b.c variable Stratix II or nCEO N.C. n MSEL[n] (3) Altera Corporation July 2004 ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Figure 4–3. FPGA Configuration in AS Mode (Serial Configuration Device Programmed by APU or Third-Party Programmer) 10 kΩ Serial Configuration Device (2) DATA DCLK nCS ASDI Notes to Figures 4–2 and 4–3: ( 3.3-V. CC (2) Serial configuration devices cannot be cascaded. ...
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... Stratix II or Cyclone Series FPGA (Master) CONF_DONE nSTATUS nCONFIG nCE nCEO n MSEL[n] (3) DATA0 DCLK nCSO ASDO Core Version a.b.c variable 1. 1. Table 4–1 to Figure 4–4 shows the AS FPGA (Slave) CONF_DONE nSTATUS nCONFIG nCE nCEO n MSEL[n] DATA0 DCLK Altera Corporation July 2004 N.C. (4) ...
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... EPCS4 Details EPCS4 524,888 bytes (4 Mbits) 8 65,536 bytes (512 Kbits) 256 2,048 256 bytes and 4–7 show the address range for each sector in the EPCS4 Address Range (Byte Addresses in HEX) Sector Start H'70000 7 H'60000 6 H'50000 5 H'40000 ...
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... Otherwise, the operation is rejected and will not be executed. 4–10 Configuration Handbook, Volume 2 Address Range (Byte Addresses in HEX) Sector Start H'18000 3 H'10000 2 H'08000 1 H'00000 0 shows the operation sequence for every operation Core Version a.b.c variable End H'1FFFF H'17FFF H'0FFFF H'07FFF Altera Corporation July 2004 ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet All attempts to access the memory contents while a write or erase cycle is in progress will not be granted, and the write or erase cycle will continue unaffected. Table 4–8. Operation Codes for Serial Configuration Devices ...
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... Write bytes operation completion Write status operation completion Erase bulk operation completion Erase sector operation completion shows the timing diagram for the write disable operation High Impedance Core Version a.b.c variable Operation Code Operation Code Altera Corporation July 2004 ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Read Status Operation The read status operation code is b'0000 0101, with the MSB listed first. You can use the read status operation to read the status register. Figures 4–7 serial configuration devices. ...
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... When any of the block protect bits are set to one, the relevant area is protected from being written by write bytes operations or erased by erase sector operations. Table 4–9. Block Protection Bits in EPCS4 Devices BP2 Bit Table 4–10. Block Protection Bits in EPCS1 ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Figure 4–9. Read Status Operation Timing Diagram nCS DCLK Operation Code ASDI High Impedance DATA Write Status Operation The write status operation code is b'0000 0001, with the MSB listed first ...
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... Additionally, it will not have any effect on the write or erase cycle in progress. 4–16 Configuration Handbook, Volume MSB Core Version a.b.c variable Status Register Figure 4–11 shows the timing Altera Corporation July 2004 ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Figure 4–11. Read Bytes Operation Timing Diagram Note to Figure 4–11: Address bits A[23..19] are don't care bits in the EPCS4 device. Address bits A[23..17] are don't care bits in the (1) EPCS1 device. Altera Corporation July 2004 Core Version a ...
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... DCLK while nCS is driven low can cause the silicon shifted out repeatedly. 4–18 Configuration Handbook, Volume 2 Table 4–11 shows the EPCS1 and EPCS4 device silicon IDs. Serial Configuration Device EPCS1 EPCS4 4–12. The device can terminate the read silicon ID operation by Core Version a ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Figure 4–12. Read Silicon ID Operation Timing Diagram Altera Corporation July 2004 Core Version a.b.c variable Configuration Handbook, Volume 2 4–19 ...
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... The device initiates the self-timed write cycle immediately after nCS is driven high. The self-timed write cycle usually takes 1.5 ms for EPCS4 devices and 2 ms for EPCS1 devices and is guaranteed to be less than 5 ms (see t amount of delay before another page of memory is written. Alternatively, the designer can check the status register’ ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Figure 4–13. Write Bytes Operation Timing Diagram Note to Figure 4–13: Address bits A[23..19] are don’t care bits in the PCS4 device. Address bits A[23..17] are the don’t care bits in (1) the EPCS1 device. ...
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... The device initiates the self-timed erase bulk cycle immediately after nCS is driven high. The self-timed erase bulk cycle usually takes 5 s for EPCS4 devices (guaranteed to be less than for EPCS1 devices (guaranteed to be less than 6 s). See t account for this delay before accessing the memory contents ...
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... Immediately after the device drives nCS high, the self-timed erase sector cycle is initiated. The self-timed erase sector cycle usually takes 2 s for EPCS1 and EPCS4 devices and is guaranteed to be less than 3 s for both serial configuration devices. You must account for this amount of delay before the memory contents can be accessed ...
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... Configuration Handbook, Volume 2 supply current when the device is in active CC parameter specifies the current when the device CC0 Table shows the timing waveform for write operation to the serial Bit n 1 Core Version a.b.c variable 4–18). t CSH Bit 0 Altera Corporation July 2004 ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Table 4–12 write operation. Table 4–12. Write Operation Parameters NCSSU t NCSH t DSU CSH t WB_EPCS1 t WB_EPCS4 EB_EPCS1 t EB_EPCS4 t ES Note to (1) Figure 4–17 device's read operation. ...
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... FPGA or embedded processor) for read bytes operation DCLK high time DCLK low time Output disable time after read Clock falling edge to data Core Version a.b.c variable ODIS Bit 0 Min Max Unit 20 MHz Altera Corporation July 2004 ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Figure 4–18 scheme using a serial configuration device. Figure 4–18. AS Configuration Timing t POR nCONFIG nSTATUS CONF_DONE nCSO DCLK Read Address ASDO t DATA0 INIT_DONE User I/O Table 4–14 Table 4–14. Timing Parameters for AS Configuration ...
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... Figure 4–2). The download cable then uses the four Altera Programming Hardware Data Sheet Programming Hardware Manufacturers USB Blaster USB Port Download Cable Development Tools Data Sheet ByteBlaster II Parallel Port Download Cable Data Sheet Core Version a.b.c variable Altera Corporation July 2004 ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Operating Tables 4–15 ratings, recommended operating conditions, DC operating conditions, Conditions and capacitance for serial configuration devices. Table 4–15. Absolute Maximum Ratings Symbol Parameter V Supply voltage input voltage GND current ...
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... OUT ° C and at a 20-MHz frequency. A Figure 4–19, the serial configuration device is an 8-pin or Table 4–20 shows the Altera serial configuration device 8-pin SOIC EPCS1 or EPCS4 Device 1 8 nCS 2 7 DATA GND shows the Altera serial configuration device 16-pin SOIC Core Version a ...
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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Figure 4–20. Altera Serial Configuration Device 16-Pin SOIC Package Pin-Out Diagram Note to (1) Table 4–20. Serial Configuration Device Pin Description Pin Name Pin Number Pin Type DATA 2 Output ASDI 5 Input nCS ...
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... EPCS64 Notes to (1) 4–32 Configuration Handbook, Volume 2 shows the ordering codes for serial configuration devices. Device Table 4–21: These devices will not be available until the second half of 2004. Core Version a.b.c variable Ordering Code EPCS1SI8N EPCS4SI8N (1) EPCS16SI16N EPCS64SI16N (1) Altera Corporation July 2004 ...