HT49R50A-1 Holtek, HT49R50A-1 Datasheet
HT49R50A-1
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HT49R50A-1 Summary of contents
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... LCD applications. The mask version HT49C50-1 and HT49C50L are fully pin and functionally compatible with the OTP version HT49R50A-1 device. The HT49C50L is a low voltage version, with the ability to operate at a minimum power supply of 1.2V, making it suitable for single cell battery applications ...
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... Block Diagram Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L 2 April 24, 2006 ...
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... Pin Assignment Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L 3 April 24, 2006 ...
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... On the port, such can be configured as CMOS output or NMOS input/output with or without pull-high resistor by options. Voltage pump for HT49R50A-1/HT49C50-1. LCD power supply for HT49C50L. LCD power supply for HT49R50A-1/HT49C50-1. Voltage pump for HT49C50L. Voltage pump SEG32 can be set as a segment common output driver for LCD panel by options ...
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... RC OSC) S Standby Current I STB7 (*f =WDT RC OSC) S Input Low Voltage for I/O V IL1 Ports, TMR and INT Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L =5V for HT49R50A-1 and HT49C50-1 Test Conditions V Conditions DD For HT49C50L LVR disable, f =4MHz SYS (for HT49R50A-1/HT49C50-1) f =8MHz SYS (for HT49R50A-1/HT49C50-1) For HT49R50A-1/HT49C50- ...
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... Low Voltage Reset Voltage LVR V Low Voltage Detector Voltage LVD Note: * for the value of VA refer to the LCD driver section. *f please refer to WDT clock option S Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Test Conditions V Conditions DD For HT49C50L For HT49R50A-1/HT49C50-1 1.5V V =0. 1.5V V =0. ...
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... System Start-up Timer Period SST t Low Voltage Width to Reset LVR t Interrupt Pulse Width INT Note 1/f , 1/f or 1/f SYS SYS1 SYS2 SYS3 Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L =5V for HT49R50A-1 and HT49C50-1 Test Conditions V Conditions DD 1.2V~2.2V (for HT49C50L) 2.2V~5.5V 3.3V~5.5V 1.2V~2.2V (for HT49C50L) 2.2V~5.5V 3.3V~5.5V 1.2V~2.2V (for HT49C50L) 2.2V~5.5V 3.3V~5.5V 1. For HT49C50L For HT49R50A-1/HT49C50-1 ...
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... Return From Subroutine Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by one. The PC then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ...
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... Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Program Memory Location 018H Location 018H is reserved for the real time clock inter- rupt service program real time clock interrupt oc- curs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018H ...
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... SET [m].i and CLR [m].i . They are also indirectly accessible through the Memory pointer register 0 (MP0;01H) or the Memory pointer register 1 (MP1;03H). Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L RAM Mapping Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write op- eration of [00H] and [02H] accesses the RAM pointed to by MP0 (01H) and MP1(03H) respectively ...
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... WDT time-out Unused bit, read as 0 Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L On entering the interrupt sequence or executing the subroutine call, the status register will not be automati- cally pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly ...
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... Real time clock request flag (1=active; 0=inactive) 7 Unused bit, read as 0 Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L INTC1), that is caused by a regular real time clock sig- nal. After the interrupt is enabled, and the stack is not full, and the RTF bit is set, a subroutine call to location 18H occurs ...
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... Of the three oscillators, if the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 24kW to 1MW for HT49R50A-1/HT49C50-1 and from 560kW to 1MW for HT49C50L. The system clock, divided available on OSC2 with pull-high resistor, which can be used to synchronize external logic ...
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... The time base time-out signal also can be applied clock source of Timer/Event Counter 1 for getting a longer timer-out period. Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Watchdog Timer Time Base Real Time Clock - RTC The real time clock (RTC) is operated in the same man- ner as the time base that is used to supply a regular in- ternal interrupt ...
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... To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Reset There are three ways in which reset may occur. RES is reset during normal operation RES is reset during HALT ...
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... PA 1111 1111 PB xxxx xxxx PC ---- 1111 Note: * refers to warm reset u means unchanged x means unknown Reset Circuit Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L RES Reset (Normal Operation) xxxx xxxx xxxx xxxx 0000 1--- 0000 1--- xxxx xxxx xxxx xxxx 0000 1--- 0000 1--- 000H 000H uuuu uuuu ...
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... The two timer/event counters are operated almost in the same manner, except the clock source and related reg- isters. Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L There are two registers related to the Timer/Event Counter 0, i.e., TMR0 ([0DH]) and TMR0C ([0EH]), and two registers related to the Timer/Event Counter 1, i.e., TMR1 ([10H], and TMR1C ([11H]) ...
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... T0ON/T1ON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only one cycle mea- Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Function TMR0C (0EH) Register Function TMR1C (11H) Register surement can be made until the T0ON/T1ON is set ...
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... After this procedure, the timer/event function can be operated normally. The ex- ample given below, using two 8-bit width Timer s (timer 0 ;timer 1) cascade into 16-bit width. Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L START: mov a, 09h ; Set ET0I & EMI bits to mov intc0, a ...
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... Note: X stands for undefined U stands for unknown Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L user wants to use the BZ/BZ or PFD function, the related PA port should be set as a CMOS output. The buzzer output signals are controlled by PA0 and PA1 data regis- ters and defined in the following table. ...
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... The output number of the LCD driver device can option (i.e., 1/2 duty, 1/3 duty or 1/4 duty). The bias type LCD driver can be R type or C type for HT49R50A-1/HT49C50-1 while the bias type LCD driver can only be C type for HT49C50L. If the R bias type is selected, no external capacitor is re- quired ...
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... Label Read/Write 0~2 RT0~RT2 R/W 3 LVDC* R/W 4 QOSC R/W 5 LVDO Note: * For HT49R50A-1/HT49C50-1 Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Reset Function multiplexer control inputs to select the real clock prescaler 111B output 0 LVD enable/disable (1/0) 32768Hz OSC quick start-up oscillating 0 0/1: quickly/slowly start LVD detection output (1/ low voltage detected ...
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... There are two types of selection: 1/2 bias or 1/3 bias for HT49R50A-1/HT49C50-1. LCD bias type selection. This option is to decide what kind of bias is selected, R type or C type for HT49R50A-1/HT49C50-1. LCD driver clock selection. There are seven types of frequency signals for the LCD driver circuits: f tion by options ...
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... Application Circuits For HT49R50A-1/HT49C50-1 Application Circuit The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator ...
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... For HT49C50L Application Circuit Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L 25 April 24, 2006 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Description 26 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Description 27 Instruction Flag Cycle Affected 2 None ...
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... Affected flag(s) TO ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF PDF PDF ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF PDF PDF addr PDF OV Z ...
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... TO 0* CPL [m] Complement data memory Description Each pin of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF PDF PDF ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Program Counter+1 PDF PDF PDF ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF PDF Program Counter+1 ...
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... Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Stack PDF Stack PDF OV Z ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF OV ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF PDF OV Z ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF PDF OV Z ...
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... Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF PDF PDF ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF PDF PDF ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L PDF PDF PDF ...
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... Package Information 48-pin SSOP (300mil) Outline Dimensions Symbol Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Dimensions in mil Min. Nom. 395 291 8 613 Max. 420 299 12 637 April 24, 2006 ...
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... QFP (14´20) Outline Dimensions Symbol Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Dimensions in mm Min. Nom. 18.50 13.90 24.50 19.90 0.65 0.30 2.50 0. Max. 19.20 14.10 25.20 20.10 3.10 3.40 1.40 0.20 7 April 24, 2006 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Dimensions in mm 330 1.0 100 0.1 13.0+0.5 0.2 2.0 0.5 32.2+0.3 0.2 38.2 0.2 43 April 24, 2006 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.1 14.2 0.1 2.0 Min. 1.5+0.25 4.0 0.1 2.0 0.1 12.0 0.1 16.20 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 44 April 24, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.10 HT49R50A-1/HT49C50-1/HT49C50L 45 April 24, 2006 ...