P8044AH InnovASIC Inc, P8044AH Datasheet
P8044AH
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P8044AH Summary of contents
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER FEATURES Form, Fit, and Function Compatible with the Intel 8044/8344 Packaging options available: 40 Pin Plastic Dual In-Line Package (PDIP), 44 Pin Plastic Leaded Chip Carrier (PLCC) 8-Bit Control Unit 8-Bit Arithmetic-Logic Unit with 16-Bit multiplication ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Package Pinout P1.0 (1) (40) IA8X44 P1.1 (2) (39) 40 Pin DIP P1.2 (3) (38) P1.3 (4) (37) P1.4 (5) (36) P1.5 (6) (35) (RTS) P1.6 (7) (34) (8) (CTS) P1.7 (33) RST (9) (32) (RXD) ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Functional Block Diagram I/O for Memory, SIU, DMA, Interrupts, Timers Port 0 ADDR/DATA/IO Memory Control XTAL Clock Gen. & Timing Reset Interrupts Copyright 2003 innovASIC The End of Obsolescence Port 2 Port 1 ADDR/DATA/IO SPCL FUNC/IO ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER I/O Characteristics The table below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. The table below provides the I/O description of ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Memory Organization Program Memory Program Memory includes interrupt and Reset vectors. The interrupt vectors are spaced at 8- byte intervals, starting from 0003H for External Interrupt 0. Reset Vectors Location Service 0003H External Interrupt 0 000BH ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Internal Memory BFh RAM Indirect Addressing 80h 7Fh 30h 2Fh 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h Internal Data Ram Copyright 2003 innovASIC The End of Obsolescence FFh Special Function Registers Addressable BITS in ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Bit Addressable Memory Both the internal RAM and the Special Function Registers have locations that are bit addressable in addition to the byte addressable locations. SFR Bit Addressable Locations Byte Address bit 7 bit 6 F0h ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Instruction Set The 8X44 architecture and instruction set are identical to the 8051’s. The following tables give a survey of the instruction set of the IA8044/IA8344 Microcontroller core. Arithmetic Operations Mnemonic ADD A,Rn Add register to ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Logic Operations Mnemonic ANL A,Rn AND register to accumulator ANL A,direct AND direct byte to accumulator ANL A,@Ri AND indirect RAM to accumulator ANL A,#data AND immediate data to accumulator ANL direct,A AND accumulator to direct ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Transfer Mnemonic MOV A,Rn Move register to accumulator MOV A,direct Move direct byte to accumulator MOV A,@Ri Move indirect RAM to accumulator MOV A,#data Move immediate data to accumulator MOV Rn,A Move accumulator to register ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Boolean Manipulation Mnemonic CLR C Clear carry flag CLR bit Clear direct bit SETB C Set carry flag SETB bit Set direct bit CPL C Complement carry flag CPL bit Complement direct bit ANL C,bit AND ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Special Function Registers The IA8044/IA8344 contains the following special function registers: Symbol Register Description ACC Accumulator B B register PSW Program Status Word SP Stack Pointer DPH Data Pointer High Byte DPL Data Pointer Low Byte ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Ports Ports P0, P1, P2 and P3 are Special Function Registers. The contents of the SFR can be observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports causes the corresponding ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER P3.7 RD External Data Memory read strobe, active LOW. This function is activated by a CPU read access from External Data Memory (i.e. MOVX A, @DPTR). P1.6 RTS Request To Send output, active low. P1.7 CTS ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Port 3 (P3): General purpose, 8-bit I/O port with pullups and auxiliary functions. Bits on this port also functions as the SIU data transmit/receive I/O, external interrupt inputs, timer inputs and the read and write strobes ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Timers/Counters Timers 0 and 1 The IA8X44 has two 16-bit timer/counter registers: Timer 0 and Timer 1. Both can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER TMOD.1 M1 TMOD.2 C/T TMOD.3 GATE TMOD.4 M0 TMOD.5 M1 TMOD.6 C/T TMOD.7 GATE Timer Mode Select Bits M1 M0 Operating Mode bit timer bit timer/counter 1 0 ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER TCON.3 IE1 TCON.4 TR0 TCON.5 TF0 TCON.6 TR1 TCON.7 TF1 Timer 0 High byte (TH0): High order byte of timer/counter0. TH0 Bit TH0.7 TH0.6 TH0.5 Timer 0 Low byte (TL0): Low order byte ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Timers/Counters Configuration Timer 0 Mode 0 OSC 12 P3.4/T0 =1 TR0 Gate 1 P3.2/INT0 Timer 0 Mode 1 Copyright 2003 innovASIC The End of Obsolescence TLO TH0 (5 BITS ) (8 BITS) C/ ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Timer 0 Mode 2 OSC 12 P3.4/T0 =1 TR0 Gate 1 P3.2/INT0 Timer 0 Mode 3 OSC 12 P3.4/T0 =1 TR0 Gate 1 P3.2/INT0 1/12 f OSC TR1 Copyright 2003 innovASIC The End of Obsolescence C/ ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Reset A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU responds by generating an internal reset, which is executed ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER General CPU Registers Accumulator (ACC): ACC is the Accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. ACC Bit ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER The state of bits RS1, RS0 selects the working registers bank as follows: RS1/0 Bank selected location 00 Bank 0 (00H – 07H) 01 Bank 1 (08H – 0FH) 10 Bank 2 (10H – 17H) 11 ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Interrupts The IA8044/IA8344 provides 5 interrupt sources. There are 2 external interrupts accessible through pins INT0 and INT1, edge or level sensitive (falling edge or low level). There are, also, internal interrupts associated with Timer 0 ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Interrupt Handling The interrupt flags are sampled during each machine cycle. The samples are polled during the next machine cycle interrupt flag is captured, the interrupt system will generate an LCALL instruction to the ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Interrupt Enable Register (IE): Contains the global interrupt enable bit and individual interrupt enable bits. Setting a bit enables the corresponding interrupt. IE Bit PCON.0 EX0 PCON.1 ET0 PCON.2 EX1 ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER SIU – Serial Interface Unit The SIU is a serial interface customized to support SDLC/HDLC protocol. As such it supports Zero Bit insertion/deletion, flags automatic access recognition and a 16 bit CRC. The SIU has two ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER SMD Select Clock Mode Bits SCM Clock Mode Externally clocked Undefined Self clocked, timer overflow Undefined Self clocked, ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER STS.6 RBE Receive buffer empty. RBE is set by the CPU when it is ready to receive a frame or has just read the buffer. RBE is cleared by the SIU when a frame has been ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Transmit Buffer Start Address Register (TBS): The TBS contains the address in internal RAM where the frame (starting with the I-field transmitted is stored. The CPU should access TBS only when the SIU is ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Receive Buffer Length Register (RBL): The RBL contains the length, in number of bytes, of the I-field storage area in internal RAM. RBL = 0 is valid (no I-field). The CPU should write RBL only when ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER DMA Count Register (FIFO): The FIFO register is actually three registers that make a three byte FIFO. These are used as temporary storage between the eight bit shift register and the receive buffer when an information ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Clocking Options The SIU may be clocked in one of two ways, with an external clock self-clocked mode. In the external clocked mode a serial clock must be provided on SCLK. This ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER station. If the response is positive the SIU interrupts the CPU. If the response is negative the SIU retransmits the frame. The SIU can send the following responses to the primary station. RR (Receive Ready), RNR ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Frame Format Options The various frame formats available with the IA8044/IA8344 are the standard SDLC format, the no control field format, the no control field and no address field format and the no FCS field format. ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Frame Format Options Frame Option NFCS Standard SDLC FLEXIBLE Mode Standard SDLC AUTO Mode No Control Field FLEXIBLE Mode No Control Field No Address Field FLEXIBLE Mode No FCS Field FLEXIBLE Mode No FCS Field AUTO ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Bit and Byte Processors BIP The BIP consists of the DPLL, NRZI encoder/decoder, serial/parallel shifter, zero insertion/deletion, shutoff logic and FCS generation/checking. The NRZI logic compares the current bit to the previous bit to determine if ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Diagnostics A diagnostic mode is included with the IA8044/IA8344 to allow testing of the SIU. Diagnostics use port pins P3.0 and P3.1. Writing P3.1 enables the diagnostic mode. When P3.1 is cleared writing ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER AC/DC Parameters Absolute Maximum Ratings: Ambient temperature under bias........................….….....-40°C to +85°C Storage temperature.......................................…........….....- 40°C to 150°C Power Supply (V )...................................……………....-0.3 to +6VDC DD Voltage on any pin to VSS...................................…..…....-0 Power dissipation...................................................................2W DC Characteristics Symbol ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER A.C. Characteristics +85 C, VDD = 5V 10%, VSS = 0V, Load Capacitance = 87pF A External Program Memory Characteristics Symbol Parameter TLHLL ALE Pulse Width TAVLL Address Valid to ALE ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Serial Interface Characteristics Symbol Parameter TDCY Data Clock TDCL Data Clock Low TDCH Data Clock High tTD Transmit Data Delay tDSS Data Setup Time tDHS Data Hold Time External Clock Drive Characteristics Symbol Parameter TCLCL Oscillator ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Waveforms Memory Access Program Memory Read Cycle TLHLL TLLPL ALE PSENn TAVLL PORT_0 INSTR. IN A7-A0 PORT_2 ADDRESS OR SFR-P2 Data Memory Read Cycle TLLDV ALE PSENn TLLWL RDn TAVDV TAVWL TLLAX PORT_0 A7-A0 PORT_2 ADDRESS ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Data Memory Write Cycle ALE PSENn TLLWL TWLWH WRn TQVWH TLLAX TAVWL TQVWX PORT_0 A7-A0 DATA OUT DATA OUT PORT_2 ADDRESS A15-A8 or SFR-P2 ADDRESS A15-A8 or SFR-P2 Serial I/O Waveforms Synchronous Data Transmission TDCL SCLK ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Packaging Information PLCC Package PIN 1 IDENTIFIER & ZONE D3 TOP VIEW 0.026-0.032 e 0.013-0.021 SIDE VIEW Copyright 2003 innovASIC The End of Obsolescence BOTTOM VIEW Package Dimensions for Symbol SEATING PLANE A ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER PDIP Package TOP LEAD 1 IDENTIFIER 1 LEAD COUNT DIRECTION SIDE VIEW (LENGTH) Copyright 2003 innovASIC The End of Obsolescence ENG210010112-00 Page Data Sheet ...
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... Cross Reference to Original Part Numbers innovASIC Part Number IA8044-PLC44I IA8044-PDW40I IA8344-PLC44I IA8344-PDW40I Copyright 2003 innovASIC The End of Obsolescence Intel Part Number N8044AH G N8044AH-R0117 G P8044 G P8044AH G P8044AH-R0117 G TP8044AH G TP8044AH-R0117 G N8344AH G TN8344AH G P8344 G P8344AH G TP8344AH G ENG210010112-00 Page Data Sheet www.innovasic.com Customer Support: 1-888-824-4184 ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER Errata Errata data listed for a particular version of the device apply only to that version. If errata data applies to more than one version it will be listed under each version affected. Errata data that ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER ISSUE: Port2 buffer bits set high are not actively driven when executing a MOVX A,@ MOVX @Ri,A instruction. During these instructions any bit that was driven low by the previous value on Port2 but ...
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IA8044/IA8344 SDLC COMMUNICATIONS CONTROLLER ISSUE: The chip does not operate properly, showing intermittent errors. Difficulty with accessing external memory. The signals used to access external memory do not have the correct timing. SOLUTION: Adjust signal timing externally if possible. ISSUE: ...