PIC16F873A Microchip Technology Inc., PIC16F873A Datasheet

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PIC16F873A

Manufacturer Part Number
PIC16F873A
Description
Manufacturer
Microchip Technology Inc.
Datasheet

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PIC16F87XA
Data Sheet
28/40/44-Pin Enhanced Flash
Microcontrollers
 2003 Microchip Technology Inc.
DS39582B

Related parts for PIC16F873A

PIC16F873A Summary of contents

Page 1

... Microchip Technology Inc. PIC16F87XA Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers DS39582B ...

Page 2

... PICmicro ® 8-bit MCUs ® code hopping EE OQ devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2003 Microchip Technology Inc. PowerInfo, Select Mode, ...

Page 3

... Parallel Slave Port (PSP) – 8 bits wide with external RD, WR and CS controls (40/44-pin only) • Brown-out detection circuitry for Brown-out Reset (BOR) Program Memory Data Device SRAM # Single Word Bytes (Bytes) Instructions PIC16F873A 7.2K 4096 192 PIC16F874A 7.2K 4096 192 PIC16F876A 14.3K 8192 368 PIC16F877A 14.3K 8192 368  ...

Page 4

... RB2 23 22 RB1 21 RB0/INT RC7/RX/DT 17 RC6/TX/CK RC5/SDO 16 RC4/SDI/SDA 15 28-Pin QFN 1 RA2/AN2/V -/CV REF REF 2 RA3/AN3/V + REF 3 RA4/T0CKI/C1OUT PIC16F873A 4 RA5/AN4/SS/C2OUT PIC16F876A OSC1/CLKI OSC2/CLKO 7 OSC2/CLKO 33 OSC1/CLKI RE2/CS/AN7 27 RE1/WR/AN6 26 RE0/RD/AN5 ...

Page 5

... RD0/PSP0 19 RD1/PSP1 20 44-Pin TQFP RC7/RX/DT 1 RD4/PSP4 2 RD5/PSP5 3 RD6/PSP6 4 PIC16F874A RD7/PSP7 PIC16F877A RB0/INT 8 RB1 9 RB2 10 11 RB3/PGM  2003 Microchip Technology Inc. 40 RB7/PGD RB6/PGC 39 38 RB5 37 RB4 RB3/PGM 36 RB2 35 34 RB1 33 RB0/INT RD7/PSP7 29 RD6/PSP6 RD5/PSP5 28 RD4/PSP4 27 ...

Page 6

... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products. DS39582B-page 4  2003 Microchip Technology Inc. ...

Page 7

... PIC16F873A • PIC16F874A • PIC16F876A • PIC16F877A PIC16F873A/876A devices are available only in 28-pin packages, while PIC16F874A/877A devices are avail- able in 40-pin and 44-pin packages. All devices in the PIC16F87XA family share common architecture with the following differences: • ...

Page 8

... PIC16F87XA FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM 13 Flash Program Memory Program 14 Bus Instruction reg Direct Addr 8 Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO MCLR Timer0 Timer1 Data EEPROM CCP1,2 Device PIC16F873A PIC16F876A Note 1: Higher order bits are from the Status register. DS39582B-page 6 ...

Page 9

... Timing Generation OSC1/CLKI OSC2/CLKO MCLR Timer0 Timer1 Data EEPROM CCP1,2 Device PIC16F874A PIC16F877A Note 1: Higher order bits are from the Status register.  2003 Microchip Technology Inc. 8 Data Bus Program Counter RAM 8 Level Stack File (13-bit) Registers (1) RAM Addr 9 Addr MUX ...

Page 10

... PIC16F87XA TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION PDIP, SOIC, QFN Pin Name SSOP Pin# Pin# 6 OSC1/CLKI 9 OSC1 CLKI OSC2/CLKO 10 7 OSC2 CLKO MCLR MCLR V PP RA0/AN0 2 27 RA0 AN0 RA1/AN1 3 28 RA1 AN1 RA2/AN2 REF CV REF RA2 AN2 V - REF CV REF RA3/AN3/V ...

Page 11

... TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED) PDIP, SOIC, QFN Pin Name SSOP Pin# Pin# RB0/INT 21 18 RB0 INT 22 19 RB1 23 20 RB2 24 21 RB3/PGM RB3 PGM 25 22 RB4 26 23 RB5 27 24 RB6/PGC RB6 PGC RB7/PGD 28 25 RB7 PGD RC0/T1OSO/T1CKI 11 8 RC0 T1OSO ...

Page 12

... A/D reference voltage (High) input I/O Digital I/O – Open-drain when configured as output. I Timer0 external clock input. O Comparator 1 output TTL I/O Digital I/O. I Analog input 4. I SPI slave select input. O Comparator 2 output. I/O = input/output P = power ST = Schmitt Trigger input Description output. REF  2003 Microchip Technology Inc. ...

Page 13

... This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.  2003 Microchip Technology Inc. QFN I/O/P Buffer Pin# ...

Page 14

... ST I/O Digital I/O. I SPI data in data I/ I/O Digital I/O. O SPI data out I/O Digital I/O. O USART asynchronous transmit. I/O USART1 synchronous clock I/O Digital I/O. I USART asynchronous receive. I/O USART synchronous data. I/O = input/output P = power ST = Schmitt Trigger input Description 2 C  2003 Microchip Technology Inc. ...

Page 15

... This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.  2003 Microchip Technology Inc. QFN I/O/P Buffer Pin# ...

Page 16

... PIC16F87XA NOTES: DS39582B-page 14  2003 Microchip Technology Inc. ...

Page 17

... On-Chip 07FFh Program Memory 0800h 0FFFh 1000h 17FFh 1800h 1FFFh PIC16F87XA PIC16F873A/874A devices have address will cause a PIC16F873A/874A PROGRAM MEMORY MAP AND STACK PC<12:0> 13 Stack Level 1 Stack Level 2 Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh ...

Page 18

... The EEPROM data memory description can 0 be found in Section 3.0 “Data EEPROM 1 and Flash Program Memory” of this data 2 sheet. 3 2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly, or indirectly, through the File Select Register (FSR).  2003 Microchip Technology Inc. ...

Page 19

... Bank 0 Unimplemented data memory locations, read as ‘0’. * Not a physical register. Note 1: These registers are not implemented on the PIC16F876A. 2: These registers are reserved; maintain these registers clear.  2003 Microchip Technology Inc. File Address (*) (*) Indirect addr. 80h TMR0 81h PCL ...

Page 20

... General Purpose Register 96 Bytes 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. * Not a physical register. Note 1: These registers are not implemented on the PIC16F873A. 2: These registers are reserved; maintain these registers clear. DS39582B-page 18 File Address (*) (*) Indirect addr. 80h TMR0 81h ...

Page 21

... Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’. 5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.  2003 Microchip Technology Inc. ...

Page 22

... Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’. 5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices. DS39582B-page 20 ...

Page 23

... Bits PSPIE and PSPIF are reserved on PIC16F873A/876A devices; always maintain these bits clear. 3: These registers can be addressed from any bank. 4: PORTD, PORTE, TRISD and TRISE are not implemented on PIC16F873A/876A devices, read as ‘0’. 5: Bit 4 of EEADRH implemented only on the PIC16F876A/877A devices.  2003 Microchip Technology Inc. ...

Page 24

... See the SUBLW and SUBWF instructions for examples. R/W-0 R-1 R-1 RP1 RP0 Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-x R/W-x R/W bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 25

... When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device  2003 Microchip Technology Inc. PIC16F87XA Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer ...

Page 26

... R/W-0 R/W-0 R/W-0 R/W-0 TMR0IE INTE RBIE TMR0IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-x INTF RBIF bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 27

... PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt Note 1: PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear. bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt ...

Page 28

... PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit read or a write operation has taken place (must be cleared in software read or write has occurred Note 1: PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear. bit 6 ADIF: A/D Converter Interrupt Flag bit A/D conversion completed ...

Page 29

... Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. PIC16F87XA Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. U-0 R/W-0 R/W-0 — ...

Page 30

... U-0 R/W-0 R/W-0 — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared  2003 Microchip Technology Inc. U-0 U-0 R/W-0 — — CCP2IF bit Master mode x = Bit is unknown ...

Page 31

... No Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. Note: BOR is unknown on Power-on Reset. It must be set by the user and checked on subsequent Resets to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a “ ...

Page 32

... BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : RETURN Therefore, manipulation of the CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0 ;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh)  2003 Microchip Technology Inc. ...

Page 33

... Bank Select Location Select 00h Data (1) Memory 7Fh Bank 0 Note 1: For register file map detail, see Figure 2-3.  2003 Microchip Technology Inc. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2. EXAMPLE 2-2: MOVLW 0x20 MOVWF FSR NEXT CLRF INCF ...

Page 34

... PIC16F87XA NOTES: DS39582B-page 32  2003 Microchip Technology Inc. ...

Page 35

... These devices have words of program Flash, with an address range from 0000h to 0FFFh for the PIC16F873A/874A and 0000h to 1FFFh for the PIC16F876A/877A. Addresses above the range of the respective device will wraparound to the beginning of program memory ...

Page 36

... Does not initiate an EEPROM read Legend Readable bit - n = Value at POR DS39582B-page 34 U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 37

... EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.  2003 Microchip Technology Inc. PIC16F87XA The steps to write to EEPROM data memory are step 10 is not implemented, check the WR bit to see if a write is in progress ...

Page 38

... MS Byte of Program Address to read ; ; LS Byte of Program Address to read ; Bank 3 ; Point to PROGRAM memory ; EE Read ; Any instructions here are ignored as program ; memory is read in second cycle after BSF EECON1,RD ; Bank Byte of Program EEDATA ; ; Byte of Program EEDATA ;  2003 Microchip Technology Inc. ...

Page 39

... First word of block to be written 14 EEADR<1:0> EEADR<1:0> Buffer Register  2003 Microchip Technology Inc. To transfer data from the buffer registers to the program memory, the EEADR and EEADRH must point to the last location in the four-word block (EEADR<1:0> = 11). Then the following sequence of events must be executed: 1. Set the EEPGD control bit (EECON1< ...

Page 40

... Disable writes ; Enable interrupts (if using) ; Bank 2 ; Increment address ; Check if lower two bits of address are ‘00’ ; Indicates when four words have been programmed ; ; Exit if more than four words, ; Continue if less than four words  2003 Microchip Technology Inc. ...

Page 41

... CMIE Legend unknown unchanged unimplemented, read as ‘0’ value depends upon condition. Shaded cells are not used by data EEPROM or Flash program memory.  2003 Microchip Technology Inc. 3.8 Operation During Code-Protect When the data EEPROM is code-protected, the micro- controller can read and write to the EEPROM normally. ...

Page 42

... PIC16F87XA NOTES: DS39582B-page 40  2003 Microchip Technology Inc. ...

Page 43

... The TRISA register controls the direction of the port pins even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.  2003 Microchip Technology Inc. PIC16F87XA EXAMPLE 4-1: INITIALIZING PORTA ...

Page 44

... Data Latch TRIS Latch Schmitt CK Q Trigger Input Buffer only Analog and (1) I/O pin (1) I/O pin Mode IP TTL Input Buffer  2003 Microchip Technology Inc. ...

Page 45

... Shaded cells are not used by PORTA. Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes, where PCFG3:PCFG0 = 0100, 0101, 011x, 1101, 1110, 1111.  2003 Microchip Technology Inc. Function Input/output or analog input. Input/output or analog input. ...

Page 46

... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). BLOCK DIAGRAM OF RB7:RB4 PINS V DD Weak P Pull-up Data Latch D Q (1) I/O pin CK TRIS Latch D Q TTL CK Input Buffer ST Buffer Latch Port EN Q3 and  2003 Microchip Technology Inc. ...

Page 47

... PORTB Data Direction Register 81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE Legend unknown unchanged. Shaded cells are not used by PORTB.  2003 Microchip Technology Inc. Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. ...

Page 48

... Peripheral Select is active I/O (1) pin and PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) RC<4:3> ( I/O (1) Q pin Schmitt Trigger Q D Schmitt Trigger EN with SMBus Levels 0 1 CKE SSPSTAT<6> and  2003 Microchip Technology Inc. ...

Page 49

... RC6 87h TRISC PORTC Data Direction Register Legend unknown unchanged  2003 Microchip Technology Inc. Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. Input/output port pin or Capture1 input/Compare1 output/ PWM1 output ...

Page 50

... I/O PORT MODE) Data Latch D Q (1) I/O pin CK TRIS Latch D Q Schmitt CK Trigger Input Buffer and Function Value on Value on: Bit 0 all other POR, BOR Resets RD0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111  2003 Microchip Technology Inc. ...

Page 51

... RE1/WR/AN6 bit 1 ST/TTL (1) RE2/CS/AN7 bit 2 ST/TTL Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.  2003 Microchip Technology Inc. FIGURE 4-9: Data Bus WR Port WR TRIS RD TRIS ...

Page 52

... Bit is set ‘0’ = Bit is cleared Value on Value on: Bit 1 Bit 0 all other POR, BOR Resets RE1 RE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 PCFG0 00-- 0000 00-- 0000 R/W-1 R/W-1 R/W-1 — Bit 2 Bit 1 Bit 0 bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 53

... Parallel Slave Port The Parallel Slave Port (PSP) is not implemented on the PIC16F873A or PIC16F876A. PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. In Slave mode asynchronously readable and writable by the external world through RD control input pin, RE0/RD/AN5, and WR control input pin, RE1/WR/AN6 ...

Page 54

... PSPIE ADIE 9Fh ADCON1 ADFM ADCS2 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F873A/876A; always maintain these bits clear. DS39582B-page ...

Page 55

... Watchdog Timer PSA WDT Enable bit Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).  2003 Microchip Technology Inc. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by ...

Page 56

... W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared ® Mid-Range MCU Family Reference Manual (DS33023) must be exe- R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 57

... Timer0 Module Register 0Bh,8Bh, INTCON GIE 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.  2003 Microchip Technology Inc. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PEIE TMR0IE INTE RBIE TMR0IF T0CS ...

Page 58

... PIC16F87XA NOTES: DS39582B-page 56  2003 Microchip Technology Inc. ...

Page 59

... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit, TMR1ON (T1CON<0>). ...

Page 60

... The prescaler, however, will continue to increment. TMR1 TMR1L TMR1ON On/Off T1SYNC 1 Prescaler T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock T1CKPS1:T1CKPS0 TMR1CS Synchronized 0 Clock Input 1 Synchronize det 2 Q Clock  2003 Microchip Technology Inc. ...

Page 61

... Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.  2003 Microchip Technology Inc. TABLE 6-1: Osc Type LP These values are for design guidance only. ...

Page 62

... CCP1IE Value on Value on: Bit 1 Bit 0 all other POR, BOR Resets INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu  2003 Microchip Technology Inc. ...

Page 63

... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. Register 7-1 shows the Timer2 Control register. Additional information on timer modules is available in ® the PICmicro Manual (DS33023). FIGURE 7-1: Sets Flag ...

Page 64

... CCP1IE Value on Value on: Bit 1 Bit 0 all other POR, BOR Resets INTF RBIF 0000 000x 0000 000u TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111  2003 Microchip Technology Inc. ...

Page 65

... The PWMs will have the same frequency and update rate (TMR2 interrupt) PWM Capture None PWM Compare None  2003 Microchip Technology Inc. PIC16F87XA CCP2 Module: Capture/Compare/PWM Register 2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is ...

Page 66

... PWM mode Legend Readable bit - n = Value at POR DS39582B-page 64 U-0 R/W-0 R/W-0 R/W-0 — CCPxX CCPxY CCPxM3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 CCPxM2 CCPxM1 CCPxM0 bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 67

... Capture and Enable Edge Detect TMR1H CCP1CON<3:0> Qs  2003 Microchip Technology Inc. 8.1.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode, or Synchro- nized Counter mode, for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. ...

Page 68

... The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1 and CCP2 modules will not set interrupt Comparator flag bit TMR1IF (PIR1<0>). TMR1L  2003 Microchip Technology Inc. ...

Page 69

... PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2  2003 Microchip Technology Inc. 8.3.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM Period = [(PR2 • 4 • T PWM frequency is defined as 1/[PWM period] ...

Page 70

... TMR1IF 0000 0000 0000 0000 — CCP2IF ---- ---0 ---- ---0 — CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu  2003 Microchip Technology Inc. ...

Page 71

... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.  2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE ...

Page 72

... PIC16F87XA NOTES: DS39582B-page 70  2003 Microchip Technology Inc. ...

Page 73

... Serial Clock (SCK) – RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) – RA5/AN4/SS/C2OUT Figure 9-1 shows the block diagram of the MSSP module when operating in SPI mode.  2003 Microchip Technology Inc. FIGURE 9-1: RC4/SDI/SDA RC5/SDO RA5/AN4/ SS/C2OUT ...

Page 74

... During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R-0 R-0 CKE D Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 75

... SPI Master mode, clock = F 0001 = SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. PIC16F87XA R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 ...

Page 76

... Example 9-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions.  2003 Microchip Technology Inc. ...

Page 77

... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1  2003 Microchip Technology Inc. 9.3.4 TYPICAL CONNECTION Figure 9-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...

Page 78

... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 2 bit 1 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2  2003 Microchip Technology Inc. ...

Page 79

... SSPIF Interrupt Flag SSPSR to SSPBUF  2003 Microchip Technology Inc. the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON< ...

Page 80

... SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39582B-page 78 bit 6 bit 5 bit 4 bit 2 bit 3 bit 6 bit 2 bit 5 bit 4 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2  2003 Microchip Technology Inc. ...

Page 81

... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on 28-pin devices; always maintain these bits clear.  2003 Microchip Technology Inc. 9.3.10 BUS MODE COMPATIBILITY Table 9-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...

Page 82

... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. When  2003 Microchip Technology Inc. ...

Page 83

... In Receive mode Data Transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data Transmit complete (does not include the ACK and Stop bits), SSPBUF is empty Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc MODE) (ADDRESS 94h) R-0 R-0 R-0 ...

Page 84

... C MODE) (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 2 /(4 * (SSPADD + 1)) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 SSPM1 SSPM0 bit 0 C conditions were not valid for x = Bit is unknown  2003 Microchip Technology Inc. ...

Page 85

... Legend Readable bit - n = Value at POR Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).  2003 Microchip Technology Inc. PIC16F87XA 2 C MODE) (ADDRESS 91h) R/W-0 R/W-0 R/W-0 ...

Page 86

... Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.  2003 Microchip Technology Inc. ...

Page 87

... The clock must be released by setting bit CKP (SSPCON<4>). See Section 9.4.4 “Clock Stretching” for more detail.  2003 Microchip Technology Inc. PIC16F87XA 9.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...

Page 88

... PIC16F87XA 2 FIGURE 9- SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39582B-page 86  2003 Microchip Technology Inc. ...

Page 89

... FIGURE 9- SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)  2003 Microchip Technology Inc. PIC16F87XA DS39582B-page 87 ...

Page 90

... PIC16F87XA 2 FIGURE 9-10 SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39582B-page 88  2003 Microchip Technology Inc. ...

Page 91

... FIGURE 9-11 SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)  2003 Microchip Technology Inc. PIC16F87XA DS39582B-page 89 ...

Page 92

... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-bit Slave Transmit mode (see Figure 9-11).  2003 Microchip Technology Inc. ...

Page 93

... SCL (see Figure 9-12). FIGURE 9-12: CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON  2003 Microchip Technology Inc Master device asserts clock Master device deasserts clock PIC16F87XA DX-1 DS39582B-page 91 ...

Page 94

... PIC16F87XA 2 FIGURE 9-13 SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39582B-page 92  2003 Microchip Technology Inc. ...

Page 95

... FIGURE 9-14 SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)  2003 Microchip Technology Inc. PIC16F87XA DS39582B-page 93 ...

Page 96

... Acknowledge (Figure 9-15). Address is compared to general call address. After ACK, set interrupt. R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’  2003 Microchip Technology Inc. ...

Page 97

... Generate a Stop condition on SDA and SCL. FIGURE 9-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision  2003 Microchip Technology Inc. Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and ...

Page 98

... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete.  2003 Microchip Technology Inc. ...

Page 99

... C interface does not conform to the 400 kHz I 100 kHz) in all details, but may be used with care where higher rates are required by the application.  2003 Microchip Technology Inc. Once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state ...

Page 100

... DX-1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h  2003 Microchip Technology Inc. ...

Page 101

... FIGURE 9-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL  2003 Microchip Technology Inc. 9.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). ...

Page 102

... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start 1st Bit T BRG  2003 Microchip Technology Inc. ...

Page 103

... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software.  2003 Microchip Technology Inc. 9.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...

Page 104

... PIC16F87XA 2 FIGURE 9-21 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39582B-page 102  2003 Microchip Technology Inc. ...

Page 105

... FIGURE 9-22 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)  2003 Microchip Technology Inc. PIC16F87XA DS39582B-page 103 ...

Page 106

... SDA sampled high. P bit (SSPSTAT<4>) is set. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition Cleared in software BRG  2003 Microchip Technology Inc. ...

Page 107

... BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF  2003 Microchip Technology Inc. 9.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...

Page 108

... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. SSP module reset into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software  2003 Microchip Technology Inc. ...

Page 109

... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF  2003 Microchip Technology Inc. SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 Set S ...

Page 110

... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG  2003 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared in software ‘0’ ...

Page 111

... SCL PEN BCLIF P SSPIF  2003 Microchip Technology Inc. The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled ...

Page 112

... PIC16F87XA NOTES: DS39582B-page 110  2003 Microchip Technology Inc. ...

Page 113

... TX9D: 9th bit of Transmit Data, can be Parity bit Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be ...

Page 114

... RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware) Legend Readable bit - n = Value at POR DS39582B-page 112 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 115

... RX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as ‘0’. Shaded cells are not used by the BRG.  2003 Microchip Technology Inc. It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the F baud rate error in some cases ...

Page 116

... F = 3.6864 MHz OSC SPBRG % value ERROR (decimal 1.2 0 191 32.9 2. 0.9 - 255 230 MHz SPBRG % value (decimal 129 255 - MHz SPBRG % value (decimal 1.71 255 0.16 64 1.72 31 1.36 21 2. 255 - 0  2003 Microchip Technology Inc. ...

Page 117

... TXEN Baud Rate CLK SPBRG Baud Rate Generator  2003 Microchip Technology Inc. enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in soft- ware. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA< ...

Page 118

... POR, BOR Resets R0IF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000  2003 Microchip Technology Inc. ...

Page 119

... RC7/RX/DT Pin Buffer and Control SPEN  2003 Microchip Technology Inc. is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the Stop bit of the third byte, if the RCREG register is still full, the Overrun Error bit, OERR (RCSTA< ...

Page 120

... POR, BOR Resets R0IF 0000 000x 0000 000u 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000  2003 Microchip Technology Inc. ...

Page 121

... RX9 ADDEN RX9 ADDEN RSR<8>  2003 Microchip Technology Inc. • Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if enable bit RCIE was set. • Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. ...

Page 122

... Value on: Bit 0 all other POR, BOR Resets R0IF 0000 000x 0000 000u 0000 0000 0000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000  2003 Microchip Technology Inc. ...

Page 123

... TSR register is empty so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible.  2003 Microchip Technology Inc. PIC16F87XA Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter ...

Page 124

... POR, BOR Resets R0IF 0000 000x 0000 000u 0000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 bit 1 bit 7 Word 2 ‘1’ bit 6 bit 7  2003 Microchip Technology Inc. ...

Page 125

... Shaded cells are not used for synchronous master reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.  2003 Microchip Technology Inc. data. Reading the RCREG register will load bit RX9D with a new value, therefore essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information ...

Page 126

... If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set bit 6 bit 7 ‘0’  2003 Microchip Technology Inc. ...

Page 127

... Baud Rate Generator Register Legend unknown unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices, always maintain these bits clear.  2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 128

... PIC16F87XA NOTES: DS39582B-page 126  2003 Microchip Technology Inc. ...

Page 129

... Channel 3 (AN3) 100 = Channel 4 (AN4) 101 = Channel 5 (AN5) 110 = Channel 6 (AN6) 111 = Channel 7 (AN7) Note: The PIC16F873A/876A devices only implement A/D channels 0 through 4; the unimplemented selections are reserved. Do not select any unimplemented channels with these devices. bit 2 GO/DONE: A/D Conversion Status bit When ADON = 1: ...

Page 130

... AN3 V 2 — — 0 AN3 AN2 6 6 AN3 V 5 AN3 AN2 4 AN3 AN2 3 AN3 AN2 2 1 AN3 AN2 1 Bit is unknown  2003 Microchip Technology Inc. ...

Page 131

... Converter V REF (Reference Voltage) V REF (Reference Voltage) Note 1: Not available on 28-pin devices.  2003 Microchip Technology Inc. 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set PEIE bit • Set GIE bit 3. Wait the required acquisition time. 4. ...

Page 132

... Sampling Switch LEAKAGE V = 0.6V T ± 500 the minimum acquisition time, , see ACQ Mid-Range MCU Family Reference SS C HOLD = DAC Capacitance = 120 Sampling Switch (k )  2003 Microchip Technology Inc. ...

Page 133

... When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for Sleep operation. 3: For extended voltage devices (LF), please refer to Section 17.0 “Electrical Characteristics”.  2003 Microchip Technology Inc. 11.3 Configuring Analog Port Pins The ADCON1 and TRIS registers control the operation of the A/D port pins ...

Page 134

... A/D result will not overwrite these locations (A/D dis- able), these registers may be used as two general purpose 8-bit registers. 10-bit Result 0 7 ADRESH 10-bit Result and a maximum ADFM = 0000 00 ADRESL Left Justified  2003 Microchip Technology Inc. ...

Page 135

... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: These registers are not available on 28-pin devices.  2003 Microchip Technology Inc. Note: For the A/D module to operate in Sleep, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To allow the con- ...

Page 136

... PIC16F87XA NOTES: DS39582B-page 134  2003 Microchip Technology Inc. ...

Page 137

... CM2:CM0: Comparator Mode bits Figure 12-1 shows the Comparator modes and CM2:CM0 bit settings. Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. The CMCON register (Register 12-1) controls the com- parator input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 12-1. ...

Page 138

... C2OUT RA2/AN2 RA5/AN4/SS/C2OUT Four Inputs Multiplexed to Two Comparators CM2:CM0 = 110 A RA0/AN0 CIS = CIS = 1 RA3/AN3 RA1/AN1 CIS = CIS = 1 RA2/AN2 REF  2003 Microchip Technology Inc. C1OUT C2OUT From Comparator V Module REF ...

Page 139

... The reference signal must be between V and V and can be applied to either SS DD pin of the comparator(s).  2003 Microchip Technology Inc. 12.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference for the compara- tors. Section 13.0 “Comparator Voltage Reference + is less IN Module” ...

Page 140

... Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. Port Pins MULTIPLEX + - CxINV  2003 Microchip Technology Inc. ...

Page 141

... R = Interconnect Resistance Source Impedance Analog Voltage  2003 Microchip Technology Inc. PIC16F87XA 12.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 12-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V ...

Page 142

... RA3 RA2 RA1 PORTA Data Direction Register Value on Value on Bit 0 all other POR Resets CM0 0000 0111 0000 0111 CVR0 000- 0000 000- 0000 RBIF 0000 000x 0000 000u -0-- 0000 -0-- 0000 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111  2003 Microchip Technology Inc. ...

Page 143

... When CVRR = 1/4 (CV REF Legend Readable bit -n = Value at POR  2003 Microchip Technology Inc. supply voltage (also referred directly from V voltage at the top of the ladder is CV where V is the saturation voltage of the power SAT switch transistor. This reference will only be as ...

Page 144

... Analog MUX Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — CVR3 CVR2 CVR1 CIS CM2 CM1 R 8R CVRR CVR3 CVR2 CVR1 CVR0 Value on Value on Bit 0 all other POR Resets CVR0 000- 0000 000- 0000 CM0 0000 0111 0000 0111  2003 Microchip Technology Inc. ...

Page 145

... It is designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry.  2003 Microchip Technology Inc. PIC16F87XA Sleep mode is designed to offer a very low current power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer wake-up or through an interrupt ...

Page 146

... EECON control 00 = 0000h to 0FFFh write-protected; 1000h to 1FFFh may be written to by EECON control For PIC16F873A/874A Write protection off; all program memory may be written to by EECON control 10 = 0000h to 00FFh write-protected; 0100h to 0FFFh may be written to by EECON control 01 = 0000h to 03FFh write-protected ...

Page 147

... PIC16F87XA C2 Note 1: See Table 14-1 and Table 14-2 for recommended values of C1 and C2 series resistor (R ) may be required for AT s strip cut crystals varies with the crystal chosen.  2003 Microchip Technology Inc. FIGURE 14-2: Clock from Ext. System TABLE 14-1: Mode XT HS 16.0 MHz These values are for design guidance only ...

Page 148

... PPM ± 50 PPM C EXT ± 50 PPM V SS ± 30 PPM ± 30 PPM Recommended values: of external ® ) and capacitor (C ) values and the EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC16F87XA OSC2/CLKO F /4 OSC 100 k EXT C > EXT  2003 Microchip Technology Inc. ...

Page 149

... On-chip 10-bit Ripple Counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.  2003 Microchip Technology Inc. PIC16F87XA state” on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during Sleep and Brown- out Reset (BOR). They are not affected by a WDT wake-up which is viewed as the resumption of normal operation ...

Page 150

... PCON and PC registers, while Table 14-6 shows the Reset conditions for all the registers. to rise to an acceptable DD falls below V DD BOR BOR falls below V for less DD BOR rises above V . The DD BOR should DD during T , the Brown-out Reset PWRT rises above V with DD BOR  2003 Microchip Technology Inc. ...

Page 151

... Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).  2003 Microchip Technology Inc. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable and is, therefore, not valid at any time. ...

Page 152

... Microchip Technology Inc. ...

Page 153

... See Table 14-5 for Reset value for specific condition. FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset  2003 Microchip Technology Inc. PIC16F87XA Power-on Reset, MCLR Resets, Brown-out Reset WDT Reset 1111 1111 1111 1111 0000 -111 0000 -111 ...

Page 154

... OST Time-out Internal Reset FIGURE 14-9: SLOW RISE TIME (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS39582B-page 152 T PWRT T PWRT VIA RC NETWORK PWRT T OST ): CASE OST ): CASE OST  2003 Microchip Technology Inc. ...

Page 155

... BCLIF BCLIE CMIF CMIE Note 1: PSP interrupt is implemented only on PIC16F874A/877A devices.  2003 Microchip Technology Inc. PIC16F87XA The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the Special Function Registers, PIR1 and PIR2 ...

Page 156

... Typically, users may wish to save key reg- isters during an interrupt (i.e., W register and Status register). This will have to be implemented in software. For the PIC16F873A/874A devices, the register W_TEMP must be defined in both Banks 0 and 1 and must be defined at the same offset from the bank base address (i ...

Page 157

... RBPU Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 14-1 for operation of these bits.  2003 Microchip Technology Inc. WDT time-out period values may be found in Section 17.0 “Electrical Characteristics” under parameter #31. Values for the WDT prescaler (actually a postscaler but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register ...

Page 158

... SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. 2 C).  2003 Microchip Technology Inc. ...

Page 159

... MCLR and RB6. This will interface to the in-circuit debugger module available from Microchip or one of the third party development tool companies.  2003 Microchip Technology Inc OST (2) T Interrupt Latency Processor in ...

Page 160

... For all other cases of low-voltage ICSP, the part may be programmed at the normal oper- ating voltage. This means calibration values, unique user IDs or user code can be reprogrammed or added. to the IHH to other PIC16CXXX on IHH  2003 Microchip Technology Inc. ...

Page 161

... A read operation is performed on a register even if the instruction writes to that register.  2003 Microchip Technology Inc. For example, a “CLRF PORTB” instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unin- tended result that the condition that sets the RBIF flag would be cleared ...

Page 162

... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk ® Mid-Range MCU  2003 Microchip Technology Inc. ...

Page 163

... Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2003 Microchip Technology Inc. BCF k Syntax: Operands: Operation: Status Affected: ...

Page 164

... Decrement f [ label ] DECF f 127 d [0,1] ( (destination) Z Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2003 Microchip Technology Inc. ...

Page 165

... Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.  2003 Microchip Technology Inc. PIC16F87XA INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d ...

Page 166

... Operation: (f) - (W) destination) Status C, DC, Z Affected: Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2003 Microchip Technology Inc. ...

Page 167

... Operation: (W) .XOR Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.  2003 Microchip Technology Inc. PIC16F87XA XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands 127 d ...

Page 168

... PIC16F87XA NOTES: DS39582B-page 166  2003 Microchip Technology Inc. ...

Page 169

... OQ - PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog 2003 Microchip Technology Inc. PIC16F87XA 16.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...

Page 170

... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high speed simulator is designed to debug, analyze and optimize time intensive DSP routines. 2003 Microchip Technology Inc. software ...

Page 171

... The PC platform and Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application. 2003 Microchip Technology Inc. PIC16F87XA 16.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...

Page 172

... PICSTART Plus development pro- grammer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion. 2003 Microchip Technology Inc. ...

Page 173

... Microcontrollers” Handbook and a USB Interface Cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. 2003 Microchip Technology Inc. 16.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...

Page 174

... PIC16F87XA NOTES: DS39582B-page 172 2003 Microchip Technology Inc. ...

Page 175

... Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin rather than pulling this pin directly PORTD and PORTE are not implemented on PIC16F873A/876A devices. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device ...

Page 176

... PIC16LF87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (6.0 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10 MHz. MAX DS39582B-page 174 PIC16F87XA Frequency PIC16LF87XA 4 MHz 10 MHz Frequency – 2.0V MHz DDAPPMIN ® 20 MHz device in the application.  2003 Microchip Technology Inc. ...

Page 177

... When BOR is enabled, the device will operate correctly until the V  2003 Microchip Technology Inc. PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...

Page 178

... When BOR is enabled, the device will operate correctly until the V DS39582B-page 176 PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...

Page 179

... When BOR is enabled, the device will operate correctly until the V  2003 Microchip Technology Inc. PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...

Page 180

... PIC16F87XA 17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) DC CHARACTERISTICS Param Sym Characteristic No. V Input Low Voltage IL I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) D033 OSC1 (in XT and LP modes) OSC1 (in HS mode) Ports RC3 and RC4: ...

Page 181

... DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. V Output Low Voltage OL D080 I/O ports D083 OSC2/CLKO (RC osc config) V Output High Voltage OH (3) D090 I/O ports D092 OSC2/CLKO (RC osc config) D150* V Open-Drain High Voltage OD Capacitive Loading Specs on Output Pins D100 ...

Page 182

... — — — — — 2k — — Max Units Comments ± – 1 — dB 400 ns PIC16F87XA 600 ns PIC16LF87XA 10 s Units Comments /32 LSb 1/2 LSb Low Range (VRR = 1) 1/2 LSb High Range (VRR = 0) —  2003 Microchip Technology Inc. ...

Page 183

... LOAD CONDITIONS Load Condition 1 Pin R = 464 for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output Note: PORTD and PORTE are not implemented on PIC16F873A/876A devices.  2003 Microchip Technology Inc ...

Page 184

... XT and RC Osc mode ns HS Osc mode s LP Osc mode ns RC Osc mode s XT Osc mode ns HS Osc mode ns HS Osc mode s LP Osc mode 4/F CY OSC ns XT oscillator s LP oscillator ns HS oscillator ns XT oscillator ns LP oscillator ns HS oscillator  2003 Microchip Technology Inc. ...

Page 185

... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKO output  2003 Microchip Technology Inc ...

Page 186

... — 1024 T — — T OSC 28 72 132 ms V — — 2.1 s 100 — —  2003 Microchip Technology Inc. 34 Conditions = 5V, -40°C to +85° 5V, -40°C to +85° OSC1 period OSC = 5V, -40°C to +85° (D005) DD BOR ...

Page 187

... Delay from External Clock Edge to Timer Increment TMR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2003 Microchip Technology Inc. PIC16F87XA ...

Page 188

... Extended(LF) 20 — 0 — CY Standard(F) 10 — Extended(LF) 20 — — Standard(F) — 10 Extended(LF) — 25 Standard(F) — 10 Extended(LF) — 25 Conditions — ns — ns — ns — ns — ns — ns — prescale value ( 16  2003 Microchip Technology Inc. ...

Page 189

... These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2003 Microchip Technology Inc. 65 Characteristic Min or CS (setup time) 20 Standard(F) ...

Page 190

... SCK (CKP = 1) SDO MSb SDI MSb In 74 Note: Refer to Figure 17-3 for load conditions. DS39582B-page 188 MSb Bit 75, 76 Bit Bit LSb 75, 76 Bit LSb LSb LSb  2003 Microchip Technology Inc. ...

Page 191

... SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb In 74 Note: Refer to Figure 17-3 for load conditions.  2003 Microchip Technology Inc MSb Bit 75, 76 Bit LSb Bit 75, 76 Bit LSb In ...

Page 192

... Units Conditions — — ns — — ns — — ns — — ns — — — — — 145 — — ns — — — Stop Condition  2003 Microchip Technology Inc. ...

Page 193

... FIGURE 17-16 BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 17-3 for load conditions.  2003 Microchip Technology Inc. Min Typ Max 100 kHz mode 4700 — — 400 kHz mode 600 — — 100 kHz mode 4000 — ...

Page 194

... After this period, the first clock pulse is generated (Note (Note Time the bus must be free before a new transmission can start bus system, but the requirement 2 C bus specification),  2003 Microchip Technology Inc. ...

Page 195

... T L2 Data Hold after CK CK DTL † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested.  2003 Microchip Technology Inc. 121 Characteristic Min Standard(F) Extended(LF) Standard(F) Extended(LF) Standard(F) ...

Page 196

... PIC16F87XA TABLE 17-14: A/D CONVERTER CHARACTERISTICS:PIC16F873A/874A/876A/877A (INDUSTRIAL) Param Sym Characteristic No. A01 N Resolution R A03 E Integral Linearity Error IL A04 E Differential Linearity Error DL A06 E Offset Error OFF A07 E Gain Error GN A10 — Monotonicity A20 V Reference Voltage (V + – V REF REF A21 V + Reference Voltage High REF A22 V - Reference Voltage Low ...

Page 197

... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES register may be read on the following T 2: See Section 11.1 “A/D Acquisition Requirements” for minimum conditions.  2003 Microchip Technology Inc. (1) 131 130 OLD_DATA Sampling Stopped is added before the A/D clock starts ...

Page 198

... PIC16F87XA NOTES: DS39582B-page 196  2003 Microchip Technology Inc. ...

Page 199

... Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 7 Minimum: mean – 3 (-40°C to +125°  2003 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC (MHz) OSC vs. F OVER V (HS MODE) OSC ...

Page 200

... DS39582B-page 198 vs. F OVER V (XT MODE) OSC DD 1500 2000 2500 F (MHz) OSC vs. F OVER V (XT MODE) OSC DD 1500 2000 2500 F (MHz) OSC 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3000 3500 4000 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3000 3500 4000  2003 Microchip Technology Inc. ...

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