PIC16F88 Microchip Technology Inc., PIC16F88 Datasheet

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PIC16F88

Manufacturer Part Number
PIC16F88
Description
Manufacturer
Microchip Technology Inc.
Datasheet

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PIC16F87/88
Data Sheet
18/20/28-Pin Enhanced Flash
Microcontrollers with
nanoWatt Technology
 2005 Microchip Technology Inc.
DS30487C

Related parts for PIC16F88

PIC16F88 Summary of contents

Page 1

... Microchip Technology Inc. PIC16F87/88 Data Sheet 18/20/28-Pin Enhanced Flash Microcontrollers with nanoWatt Technology DS30487C ...

Page 2

... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. , microID, MPLAB, PIC, PICmicro, PICSTART, ® 8-bit MCUs ® code hopping EE OQ  2005 Microchip Technology Inc. ...

Page 3

... Comparator outputs are externally accessible Program Memory Device Flash # Single-Word SRAM (bytes) Instructions (bytes) PIC16F87 7168 4096 368 PIC16F88 7168 4096 368  2005 Microchip Technology Inc. PIC16F87/88 Pin Diagram 18-Pin PDIP, SOIC RA2/AN2/CV RA3/AN3/V RA4/AN4/T0CKI/ RA5/MCLR/V RB0/INT/CCP1 RB1/SDI/SDA ...

Page 4

... RA6/OSC2/CLKO (1) RB7/AN6/PGD/T1OSI RB6/AN5/PGC/T1OSO/T1CKI 8 11 RB5/SS/TX/CK (1) RB4/SCK/SCL RA1/AN1 1 20 REF 2 19 RA0/AN0 3 18 RA7/OSC1/CLKI RA6/OSC2/CLKO (1) RB7/AN6/PGD/T1OSI 7 14 RB6/AN5/PGC/T1OSO/T1CKI 8 13 RB5/SS/TX/ (1) RB4/SCK/SCL 11 10  2005 Microchip Technology Inc. ...

Page 5

... The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.  2005 Microchip Technology Inc RA7/OSC1/CLKI 20 2 RA6/OSC2/CLKO PIC16F87 RB7/PGD/T1OSI 15 7 RB6/PGC/T1OSO/T1CKI 21 1 RA7/OSC1/CLKI 2 20 RA6/OSC2/CLKO PIC16F88 RB7/AN6/PGD/T1OSI 7 15 RB6/AN5/PGC/T1OSO/T1CKI PIC16F87/88 DS30487C-page 3 ...

Page 6

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS30487C-page 4  2005 Microchip Technology Inc. ...

Page 7

... These functions include: • External Interrupt • Change on PORTB Interrupt • Timer0 Clock Input • Low-Power Timer1 Clock/Oscillator • Capture/Compare/PWM • 10-bit, 7-channel A/D Converter (PIC16F88 only) 2 • SPI™/I C™ • Two Analog Comparators • AUSART • MCLR (RA5) can be configured as an input Table 1-2 details the pinout of the devices with descriptions and details for each pin ...

Page 8

... Addr FSR reg STATUS reg 3 MUX ALU 8 W reg Timer0 SSP Data EE Comparators 256 Bytes PORTA RA0/AN0 RA1/AN1 RA2/AN2/CV REF RA3/AN3/C1OUT RA4/T0CKI/C2OUT RA5/MCLR/V PP RA6/OSC2/CLKO RA7/OSC1/CLKI PORTB (2) RB0/INT/CCP1 RB1/SDI/SDA RB2/SDO/RX/DT (2) RB3/PGM/CCP1 RB4/SCK/SCL RB5/SS/TX/CK RB6/PGC/T1OSO/T1CKI RB7/PGD/T1OSI  2005 Microchip Technology Inc. ...

Page 9

... FIGURE 1-2: PIC16F88 DEVICE BLOCK DIAGRAM 13 Program Counter Flash Program Memory 8 Level Stack (13-bit) Program 14 Bus Instruction reg Direct Addr 8 Power-up Timer Instruction Oscillator Start-up Timer Decode & Control Power-on Reset Timing Watchdog Generation Timer OSC1/CLKI Brown-out OSC2/CLKO Reset RA5/MCLR Timer2 ...

Page 10

... This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 4: PIC16F88 devices only. 5: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register. DS30487C-page 8 QFN ...

Page 11

... This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 4: PIC16F88 devices only. 5: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.  2005 Microchip Technology Inc. ...

Page 12

... PIC16F87/88 NOTES: DS30487C-page 10  2005 Microchip Technology Inc. ...

Page 13

... For example, the same instruction will be accessed at locations 020h, 420h, 820h, C20h, 1020h, 1420h, 1820h and 1C20h. The Reset vector is at 0000h and the interrupt vector is at 0004h.  2005 Microchip Technology Inc. PIC16F87/88 FIGURE 2-1: PROGRAM MEMORY MAP AND STACK: PIC16F87/88 PC<12:0> ...

Page 14

... EECON1 18Ch EECON2 10Dh 18Dh (1) 10Eh Reserved 18Eh (1) 10Fh 18Fh Reserved 110h 190h General Purpose Register 16 Bytes 19Fh 11Fh 1A0h 120h General Purpose Register 80 Bytes 16Fh 1EFh 170h 1F0h accesses 70h-7Fh 17Fh 1FFh Bank 3  2005 Microchip Technology Inc. ...

Page 15

... FIGURE 2-3: PIC16F88 REGISTER FILE MAP File Address (*) Indirect addr. Indirect addr. 00h TMR0 01h OPTION_REG 02h PCL 03h STATUS STATUS FSR 04h 05h PORTA 06h PORTB 07h 08h 09h 0Ah PCLATH PCLATH INTCON 0Bh INTCON PIR1 0Ch 0Dh PIR2 0Eh TMR1L ...

Page 16

... Indirect Data Memory Address Pointer 05h PORTA PORTA Data Latch when written; PORTA pins when read (PIC16F87) PORTA Data Latch when written; PORTA pins when read (PIC16F88) 06h PORTB PORTB Data Latch when written; PORTB pins when read (PIC16F87) PORTB Data Latch when written; PORTB pins when read (PIC16F88) 07h — ...

Page 17

... These registers can be addressed from any bank. 3: RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’. 4: PIC16F88 device only.  2005 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 ...

Page 18

... FSR Indirect Data Memory Address Pointer 105h WDTCON — — 106h PORTB PORTB Data Latch when written; PORTB pins when read (PIC16F87) PORTB Data Latch when written; PORTB pins when read (PIC16F88) 107h — Unimplemented 108h — Unimplemented 109h — Unimplemented ...

Page 19

... Legend Readable bit -n = Value at POR  2005 Microchip Technology Inc. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged recommended, therefore, that only BCF, BSF, SWAPF ...

Page 20

... W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2005 Microchip Technology Inc. ...

Page 21

... At least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state Legend Readable bit -n = Value at POR  2005 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

Page 22

... Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. bit 5 RCIE: AUSART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TXIE: AUSART Transmit Interrupt Enable bit ...

Page 23

... ADIF: A/D Converter Interrupt Flag bit 1 = The A/D conversion completed (must be cleared in software The A/D conversion is not complete Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. bit 5 RCIF: AUSART Receive Interrupt Flag bit 1 = The AUSART receive buffer is full (cleared by reading RCREG) ...

Page 24

... Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR DS30487C-page 22 U-0 R/W-0 U-0 U-0 — EEIE — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared  2005 Microchip Technology Inc. U-0 U-0 — — bit Bit is unknown ...

Page 25

... The write operation completed (must be cleared in software The write operation is not complete or has not been started bit 3-0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR  2005 Microchip Technology Inc. U-0 R/W-0 CMIF — EEIF W = Writable bit U = Unimplemented bit, read as ‘0’ ...

Page 26

... BOREN bit in the Configuration Word register). U-0 U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-0 R/W-x — POR BOR bit Bit is unknown  2005 Microchip Technology Inc. ...

Page 27

... PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).  2005 Microchip Technology Inc. Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP ...

Page 28

... Bank Select 80h 100h 180h FFh 17Fh 1FFh Bank 1 Bank 2 Bank 3 INDIRECT ADDRESSING ;initialize pointer ;to RAM INDF ;clear INDF register FSR, F ;inc pointer NEXT ;no clear next ;yes continue Indirect Addressing 7 0 FSR Register Location Select  2005 Microchip Technology Inc. ...

Page 29

... Microchip Technology Inc. PIC16F87/88 When the device is code-protected, the CPU may continue to read and write the data EEPROM memory. ...

Page 30

... Does not initiate an EEPROM read Legend Readable bit -n = Value at POR DS30487C-page 28 U-0 U-0 R/W-x R/W-x — — FREE WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ Set only ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown  2005 Microchip Technology Inc. ...

Page 31

... EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.  2005 Microchip Technology Inc. PIC16F87/88 The steps to write to EEPROM data memory are step 10 is not implemented, check the WR bit to see if a write is in progress ...

Page 32

... WREN bit to enable writes and set FREE bit to enable the erase. 3. Disable interrupts. 4. Write 55h to EECON2. 5. Write AAh to EECON2. 6. Set the WR bit. This will begin the row erase cycle. 7. The CPU will stall for duration of the erase.  2005 Microchip Technology Inc. ...

Page 33

... EECON1, WR NOP NOP BCF EECON1, FREE BCF EECON1, WREN BSF INTCON, GIE  2005 Microchip Technology Inc. ; Select Bank of EEADRH ; ; MS Byte of Program Address to Erase ; ; LS Byte of Program Address to Erase ; Select Bank of EECON1 ; Point to PROGRAM memory ; Enable Write to memory ; Enable Row Erase operation ...

Page 34

... After each long write, the 4 buffer registers will be reset to 3FFF EEDATH EEDATA EEADR<1:0> Buffer Register Buffer Register Program Memory WR” instruction, if WR” instruction, if transfer the data from 0 All buffers are transferred to Flash automatically after this word is written 14 EEADR<1:0> Buffer Register  2005 Microchip Technology Inc. ...

Page 35

... GOTO loop BANKSEL EECON1 BCF EECON1, WREN BSF INTCON,GIE  2005 Microchip Technology Inc. ;prepare for WRITE procedure ;point to program memory ;allow write cycles ;perform write only ;prepare for 4 words to be written ;Start writing at 0x100 ;load HIGH address ;load LOW address ...

Page 36

... FREE WRERR WREN WR — EEIF — — — — EEIE — — — Value on Value on Bit 0 Power-on all other Reset Resets xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu RD x--x x000 x--x q000 ---- ---- ---- ---- — 00-0 ---- 00-0 ---- — 00-0 ---- 00-0 ----  2005 Microchip Technology Inc. ...

Page 37

... AT strip S cut crystals varies with the crystal chosen (typically F between  2005 Microchip Technology Inc. TABLE 4-1: Osc Type Capacitor values are for design guidance only. These capacitors were tested with the crystals listed /4 OSC below for basic start-up and operation ...

Page 38

... PORTA (RA6). Figure 4-3 shows the pin connections for the ECIO Oscillator mode. To Internal FIGURE 4-3: Logic Clock from Ext. System . OSC2 for DD is 330 EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC16F87/88 RA6 I/O (OSC2)  2005 Microchip Technology Inc. ...

Page 39

... RA6 Recommended values EXT C > EXT  2005 Microchip Technology Inc. 4.5 Internal Oscillator Block The PIC16F87/88 devices include an internal oscillator block which generates two different clock signals; either can be used as the system’s clock source. This ) val- can eliminate the need for external oscillator circuits on EXT the OSC1 and/or OSC2 pins ...

Page 40

... WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency. U-0 R/W-0 R/W-0 R/W-0 — TUN5 TUN4 TUN3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 TUN2 TUN1 TUN0 bit Bit is unknown  2005 Microchip Technology Inc. ...

Page 41

... When the bits are cleared (SCS<1:0> = 00), the system clock source comes from the main oscillator that is selected by the  2005 Microchip Technology Inc. PIC16F87/88 FOSC2:FOSC0 configuration bits in Configuration Word 1 register. When the bits are set in any other ...

Page 42

... Watchdog Timer to the start of execution at the new clock frequency. R/W-0 R/W-0 R-0 R/W-0 (1) IRCF1 IRCF0 OSTS IOFS ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared  2005 Microchip Technology Inc. R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown ...

Page 43

... Caution must be taken when modifying the IRCF bits using BCF or BSF instructions possible to modify the IRCF bits to a frequency that may be out of the V ification range; for example, V and IRCF = 111 (8 MHz).  2005 Microchip Technology Inc. LP, XT, HS, RC Timer1 OSCCON<6:4> 8 MHz 111 ...

Page 44

... POR, CPU start-up is invoked to allow the CPU to become ready for code execution. 1024 Clock Cycles Following a change from INTRC, an OST (OST) of 1024 cycles must occur. Refer to Section 4.6.4 “Modifying the 4 ms (approx.) IRCF Bits” for further details.  2005 Microchip Technology Inc. ...

Page 45

... DLY INP  2005 Microchip Technology Inc. PIC16F87/88 If the system clock does not come from the INTRC (31.25 kHz) when the SCS bits are changed and the IRCF bits in the OSCCON register are configured for a frequency other than INTRC, the frequency may not be stable immediately. The IOFS bit (OSCCON< ...

Page 46

... A clock switching event will occur if the final state of the SCS bits is different from the original (3) T SCS PC +1 Modified Final SCS<1:0> SCS<1:0> 00 – no change 01 10 – INTRC 11 10 – no change 11 00 – Oscillator 01 defined by FOSC<2:0>  2005 Microchip Technology Inc. ...

Page 47

... If the primary system clock is either RC or EC, an internal delay timer (5-10 s) will suspend operation after exiting Secondary Clock mode to allow the CPU to become ready for code execution.  2005 Microchip Technology Inc. PIC16F87/88 4.7.3.1 Returning to Primary Clock Source Sequence Changing back to the primary oscillator from SEC_RUN or RC_RUN can be accomplished by either changing SCS< ...

Page 48

... INP minimum. OSC SCS INP DLY INP DS30487C-page 46 P (1) INP ( SCS (4) OSC ( (5) T DLY  2005 Microchip Technology Inc. ...

Page 49

... OSC 5- MHz system clock). CPU  2005 Microchip Technology Inc. no oscillator start-up time required because the primary clock is already stable; however, there is a delay between the wake-up event and the following Q2. An internal delay timer of 5-10 s will suspend operation after the Reset to allow the CPU to become ready for code execution ...

Page 50

... CPU (2) T CPU Start-up System Clock MCLR OSTS Program PC Counter Note 30. 5- MHz system clock). CPU DS30487C-page 0001h 0000h 0002h 0003h 0004h  2005 Microchip Technology Inc. ...

Page 51

... LP, XT, HS 1024 Clocks 00 (Due to Reset) (OST) LP, XT, HS Note 1: If the new clock source is the INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms (approx.) after the clock change.  2005 Microchip Technology Inc. OSTS IOFS T1RUN System Bit Bit Bit ...

Page 52

... If the primary oscillator is XT HS, the core will continue to run off T1OSC and execute the SLEEP command. When Sleep is exited, the part will resume operation with the primary oscillator after the OST has expired.  2005 Microchip Technology Inc. ...

Page 53

... PIC16F88 only.  2005 Microchip Technology Inc. Pin RA4 is multiplexed with the Timer0 module clock input. On PIC16F88 devices also multiplexed with an analog input to become the RA4/AN4/T0CKI/ C2OUT pin. The RA4/AN4/T0CKI/C2OUT pin is a Schmitt Trigger input and full CMOS output driver. ...

Page 54

... Shaded cells are not used by PORTA. Note 1: This value applies only to the PIC16F87. 2: This value applies only to the PIC16F88. 3: Pin input only; the state of the TRISA5 bit has no effect and will always read ‘1’. 4: PIC16F88 device only ...

Page 55

... Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA To Comparator To A/D Module V - (PIC16F88 only) REF To A/D Module Channel Input (PIC16F88 only)  2005 Microchip Technology Inc. +/C1OUT PIN REF Comparator Mode = 110 Analog Input Mode Q + Input (PIC16F88 only) REF /V - PIN REF REF Q EN ...

Page 56

... Q Comparator 2 Output WR PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA TMR0 Clock Input To A/D Module Channel Input (PIC16F88 only) FIGURE 5-5: BLOCK DIAGRAM OF RA5/MCLR/V MCLRE MCLR Circuit Data Bus V RD TRIS SS RD Port DS30487C-page Analog Input Mode Q EN PIN ...

Page 57

... WR PORTA CK Q Data Latch TRISA TRIS Latch RD TRISA Q RD PORTA Note 1: I/O pins have protection diodes CLKO signal is 1/4 of the F  2005 Microchip Technology Inc. From OSC1 Oscillator Circuit 1x0, 011) OSC V SS Schmitt Trigger ...

Page 58

... CK Q TRIS Latch RD TRISA Q RD PORTA Note 1: I/O pins have protection diodes to V DS30487C-page 56 Oscillator Circuit (F = 011) OSC 10x OSC V SS Schmitt Trigger Input Buffer 10x OSC and (1) RA7/OSC1/CLKI pin V SS  2005 Microchip Technology Inc. ...

Page 59

... Any read or write of PORTB. This will end the mismatch condition. b) Clear flag bit RBIF.  2005 Microchip Technology Inc. PIC16F87/88 A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. ...

Page 60

... ANS6 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by PORTB. Note 1: This value applies only to the PIC16F87. 2: This value applies only to the PIC16F88. DS30487C-page 58 Function (1) Input/output pin or external interrupt input. Capture input/Compare output/PWM output pin. Internal software programmable weak pull-up. ...

Page 61

... WR TRISB To INT0 or CCP Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register.  2005 Microchip Technology Inc. (3) PIN 0 CCP1M<3:0> = 000 ...

Page 62

... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The SDA Schmitt conforms to the I DS30487C-page TRISB Q Schmitt Trigger Buffer and specification Weak P Pull- (1) I/O pin TTL Input Buffer PORTB  2005 Microchip Technology Inc. ...

Page 63

... SDO 1 0 (2) RBPU Data Bus WR PORTB WR TRISB DT Drive RX/DT Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.  2005 Microchip Technology Inc. SPEN Data Latch TRIS Latch ...

Page 64

... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The CCP1 pin is determined by the CCPMX bit in Configuration Word 1 register. DS30487C-page 62 (3) PIN CCP1M<3:0> = 0100, 0101, 0110, 0111 and CCPMX = LVP = Weak P Pull-up (1) I/O pin TTL Input Buffer PORTB and  2005 Microchip Technology Inc. ...

Page 65

... From other RB7:RB4 pins SCK SCL Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: The SCL Schmitt conforms to the I  2005 Microchip Technology Inc SCL Drive (3) and V ...

Page 66

... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS30487C-page 64 Data Latch TRIS Latch Latch Q Q and Weak P Pull-up (1) I/O pin TTL Input Buffer PORTB EN Q3  2005 Microchip Technology Inc. ...

Page 67

... T1OSCEN/ICD/PROG Mode Set RBIF From other RB7:RB4 pins PGC/T1CKI From T1OSCO Output To A/D Module Channel Input (PIC16F88 only) Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: PIC16F88 devices only.  2005 Microchip Technology Inc. ...

Page 68

... PGD DRVEN RD PORTB Set RBIF From other RB7:RB4 pins PGD To T1OSCI Input To A/D Module Channel Input (PIC16F88 only) Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 3: PIC16F88 devices only. DS30487C-page 66 ...

Page 69

... Prescaler WDT Enable bit Note: T0CS, T0SE, PSA and PS2:PS0 bits are (OPTION_REG<5:0>).  2005 Microchip Technology Inc. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will incre- ment, either on every rising or falling edge of pin RA4/ T0CKI/C2OUT. The incrementing edge is determined by ...

Page 70

... W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared ® Mid-Range MCU Family Reference Manual” (DS33023) must be to Timer0, will clear the R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 bit Bit is unknown  2005 Microchip Technology Inc. ...

Page 71

... Timer0 Module Register 0Bh,8Bh, INTCON GIE 10Bh,18Bh 81h,181h OPTION_REG RBPU INTEDG Legend unknown unchanged. Shaded cells are not used by Timer0.  2005 Microchip Technology Inc. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PEIE TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x T0CS T0SE ...

Page 72

... PIC16F87/88 NOTES: DS30487C-page 70  2005 Microchip Technology Inc. ...

Page 73

... Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead.  2005 Microchip Technology Inc. PIC16F87/88 7.1 Timer1 Operation Timer1 can operate in one of three modes: • ...

Page 74

... TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RB6/AN5 0 = Internal clock (F Note 1: Available on PIC16F88 devices only. bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend Readable bit ...

Page 75

... TMR1H T1OSC T1OSO/T1CKI T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.  2005 Microchip Technology Inc. 7.4 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of ...

Page 76

... This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. The example codes provided in Example 7-1 Example 7-2 demonstrate how to write to and read Timer1 while it is running in Asynchronous mode.  2005 Microchip Technology Inc. and ...

Page 77

... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 7-1 for additional information about capacitor selection.  2005 Microchip Technology Inc. PIC16F87/88 TABLE 7-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests this value as a starting point in validating the oscillator circuit ...

Page 78

... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times.  2005 Microchip Technology Inc. ...

Page 79

... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.  2005 Microchip Technology Inc. ; Preload TMR1 register pair ; for 1 second overflow ...

Page 80

... PIC16F87/88 NOTES: DS30487C-page 78  2005 Microchip Technology Inc. ...

Page 81

... Additional information on timer modules is available in ® the “PICmicro Mid-Range MCU Family Reference Manual” (DS33023).  2005 Microchip Technology Inc. 8.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • A write to the TMR2 register • ...

Page 82

... PR2 Timer2 Period Register Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. DS30487C-page 80 R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘0’ ...

Page 83

... TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend Readable bit -n = Value at POR  2005 Microchip Technology Inc. The CCP module’s input/output pin (CCP1) can be configured as RB0 or RB3. This selection is set in bit 12 (CCPMX) of the Configuration Word. Additional information on the CCP module is available ® ...

Page 84

... EXAMPLE 9-1: CLRF CCP1CON MOVLW NEW_CAPT_PS ;Load the W reg with MOVWF CCP1CON CCPR1L TMR1L CHANGING BETWEEN CAPTURE PRESCALERS ;Turn CCP module off ;the new prescaler ;move value and CCP ON ;Load CCP1CON with this ;value  2005 Microchip Technology Inc. ...

Page 85

... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.  2005 Microchip Technology Inc. 9.2.1 CCP PIN CONFIGURATION The user must configure the CCP1 pin as an output by clearing the TRISB< ...

Page 86

... PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. • OSC (TMR2 Prescale Value) T • (TMR2 Prescale Value) OSC  2005 Microchip Technology Inc. ...

Page 87

... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.  2005 Microchip Technology Inc. 9.3.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...

Page 88

... PIC16F87/88 NOTES: DS30487C-page 86  2005 Microchip Technology Inc. ...

Page 89

... Family Reference (DS33023). Refer to Application Note AN578, “Use of the SSP 2 Module in the I C™ Multi-Master Environment” (DS00578).  2005 Microchip Technology Inc. 10.2 SPI Mode This section contains operational characteristics of the SPI module. SPI mode allows 8 bits of data to be synchronously transmitted ...

Page 90

... C mode only mode only mode only mode only modes): C mode only Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-0 (1) R bit Bit is unknown  2005 Microchip Technology Inc. ...

Page 91

... C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1000, 1001, 1010, 1100, 1101 = Reserved Legend Readable bit -n = Value at POR  2005 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) SSPEN CKP SSPM3 ...

Page 92

... Shaded cells are not used by the SSP in SPI™ mode. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. DS30487C-page 90 To enable the serial port, SSP Enable bit, SSPEN (SSPCON< ...

Page 93

... SSPIF FIGURE 10-4: SPI™ MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit 7 bit 6 SDI (SMP = 0) bit 7 SSPIF  2005 Microchip Technology Inc. bit 6 bit 5 bit 3 bit 4 bit 6 bit 5 bit 3 bit 4 bit 2 bit 5 bit 4 bit 3 PIC16F87/88 ...

Page 94

... C Slave mode pins (PORTx [SDA, SCL communication pins communica opera modes to be selected mode, with the SSPEN bit set module operation may be ® Mid-Range MCU Family  2005 Microchip Technology Inc. ...

Page 95

... For a 10-bit address, the first byte would equal ‘1111 0’, where A9 and A8 are the two MSbs of the address.  2005 Microchip Technology Inc. PIC16F87/88 The sequence of events for 10-bit Address mode is as follows, with steps 7-9 for slave transmitter: 1 ...

Page 96

... Yes Yes Yes Receiving Data ACK Bus master terminates transfer ACK is not sent Transmitting Data ACK From SSP Interrupt Service Routine  2005 Microchip Technology Inc. ...

Page 97

... Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in SPI™ mode. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87 Maintain these bits clear in I C™ mode. ...

Page 98

... PIC16F87/88 NOTES: DS30487C-page 96  2005 Microchip Technology Inc. ...

Page 99

... TSR full bit 0 TX9D: 9th bit of Transmit Data, can be Parity bit Legend Readable bit -n = Value at POR  2005 Microchip Technology Inc. The AUSART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) Bit SPEN (RCSTA< ...

Page 100

... RX9D: 9th bit of Received Data (can be Parity bit, but must be calculated by user firmware) Legend Readable bit -n = Value at POR DS30487C-page 98 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown  2005 Microchip Technology Inc. ...

Page 101

... SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as ‘0’. Shaded cells are not used by the BRG.  2005 Microchip Technology Inc. 11.1.1 AUSART AND INTRC OPERATION The PIC16F87/88 has an 8 MHz INTRC that can be used as the system clock, thereby eliminating the need for external components to provide the clock source ...

Page 102

... MHz SPBRG % value (decimal) — — 129 — 255 — MHz SPBRG % value (decimal) — — — — 255 64 31 -1.36 21 -2.10 18 -1.36 10 — 255 — 0  2005 Microchip Technology Inc. ...

Page 103

... NA — — 1.202 2.4 2.404 +0.16 207 2.404 9.6 9.615 +0.16 51 9.615 19.2 19.231 +0.16 25 19.231 28.8 29.412 +2.12 16 27.778 38.4 38.462 +0.16 12 35.714 57.6 55.556 -3.55 8 62.500  2005 Microchip Technology Inc MHz MHz OSC OSC SPBRG % % value ERROR KBAUD ERROR (decimal) 0 207 0.300 0 +0.16 51 1.202 +0.16 +0.16 25 2.404 +0.16 -6.99 6 10.417 +8.51 +8. — ...

Page 104

... TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register. Data Bus TXREG Register 8 LSb Pin Buffer 0 and Control TSR Register TRMT TX9 TX9D RB5/SS/TX/CK pin SPEN  2005 Microchip Technology Inc. ...

Page 105

... Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.  2005 Microchip Technology Inc 9-bit transmission is desired, then set transmit bit TX9 ...

Page 106

... RX9 Data Recovery RX9D RCIF Interrupt RCIE Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG FERR RSR Register LSb 1 0 Start RCREG Register FIFO 8 Data Bus Start bit bit 7/8 Stop bit  2005 Microchip Technology Inc. ...

Page 107

... Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.  2005 Microchip Technology Inc. 6. Flag bit RCIF will be set when reception is com- plete and an interrupt will be generated if enable bit RCIE is set ...

Page 108

... CPU. OERR CREN 64 RSR Register MSb Stop (8) Data RX9 Recovery Enable Load of Receive Buffer RX9D RCREG Register 8 RCIF Interrupt RCIE  2005 Microchip Technology Inc. FERR LSb 0 1 Start 8 8 FIFO Data Bus ...

Page 109

... Baud Rate Generator Register Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.  2005 Microchip Technology Inc. Start bit 8 ...

Page 110

... Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.  2005 Microchip Technology Inc. ...

Page 111

... Legend unknown unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. FIGURE 11-9: SYNCHRONOUS TRANSMISSION Q1Q2 Q1Q2Q3 Q4Q1Q2 Q3 Q4Q1 ...

Page 112

... Legend unknown unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. DS30487C-page 110 receive data. Reading the RCREG register will load bit ...

Page 113

... Shaded cells are not used for synchronous slave transmission. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.  2005 Microchip Technology Inc Q4Q1 Q4Q1 Q4Q1 ...

Page 114

... Legend unknown unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. DS30487C-page 112 When setting up a synchronous slave reception, follow these steps: 1 ...

Page 115

... REF The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To oper- ate in Sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. REGISTER 12-1: ANSEL: ANALOG SELECT REGISTER (ADDRESS 9Bh) PIC16F88 DEVICES ONLY U-0 R/W-1 — ANS6 bit 7 bit 7 Unimplemented: Read as ‘ ...

Page 116

... PIC16F87/88 REGISTER 12-2: ADCON0: A/D CONTROL REGISTER (ADDRESS 1Fh) PIC16F88 DEVICES ONLY R/W-0 R/W-0 ADCS1 ADCS0 bit 7 bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits If ADCS2 = OSC OSC /32 OSC (clock derived from the internal A/D module RC oscillator ADCS2 = OSC /16 ...

Page 117

... REGISTER 12-3: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) PIC16F88 DEVICES ONLY R/W-0 R/W-0 ADFM ADCS2 bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’ Left justified. Six Least Significant bits of ADRESL are read as ‘0’. bit 6 ...

Page 118

... T required before the next acquisition starts. CHS2:CHS0 110 101 100 011 010 V IN 001 000 AV DD VCFG1:VCFG0 AV SS VCFG1:VCFG0 . A minimum wait RB7/AN6/PGD/T1OSI RB6/AN5/PGC/T1OSO/T1CKI RA4/AN4/T0CKI/C2OUT RA3/AN3/V +/C1OUT REF RA2/AN2/ REF REF RA1/AN1 RA0/AN0  2005 Microchip Technology Inc. ...

Page 119

... Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance (from DAC) HOLD  2005 Microchip Technology Inc. acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate Equation 12-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D) ...

Page 120

... If the power-managed mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected ADCS<1:0> time but can vary between 2 Maximum Device Frequency Max. 1.25 MHz 2.5 MHz 5 MHz 10 MHz 20 MHz 20 MHz (Note 1)  2005 Microchip Technology Inc. ...

Page 121

... ADRESH ADRESL 10-bit Result Right Justified  2005 Microchip Technology Inc. 12.5 A/D Conversions Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL ...

Page 122

... TRISB7 TRISB6 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87. 2: PIC16F88 only. 3: Pin input only; the state of the TRISA5 bit has no effect and will always read ‘1’. ...

Page 123

... connects to RA0 connects to RA1 IN bit 2-0 CM<2:0>: Comparator Mode bits Legend Readable bit -n = Value at POR  2005 Microchip Technology Inc. The CMCON register (Register 13-1) controls the comparator input and output multiplexors. A block two analog diagram of the various comparator configurations is shown in Figure 13-1. R-0 R/W-0 R/W-0 R/W-0 ...

Page 124

... Off C2 (Read as ‘0’ CIS = CIS = 1 C1OUT CIS = CIS = 1 C2OUT From V Module REF C1OUT C2OUT CIS = CIS = 1 C1OUT C2OUT  2005 Microchip Technology Inc. ...

Page 125

... The reference signal must be between V and V and can be applied to either SS DD pin of the comparator(s).  2005 Microchip Technology Inc. 13.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated comparators. Section 14.0 “Comparator Voltage + is less IN Reference Module” ...

Page 126

... Any read or write of CMCON will end the mismatch condition. b) Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared. Port Pins MULTIPLEX CnINV RD_CMCON  2005 Microchip Technology Inc. ...

Page 127

... R = Interconnect Resistance Source Impedance Analog Voltage  2005 Microchip Technology Inc. PIC16F87/88 13.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 13-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and V ...

Page 128

... PIE2 OSFIE CMIE 05h PORTA RA7 RA6 (PIC16F87) (PIC16F88) 85h TRISA TRISA7 TRISA6 TRISA5 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the comparator module. Note 1: Pin input only; the state of the TRISA5 bit has no effect and will always read ‘1’. ...

Page 129

... This reference will only be as accurate as the values of CV The output of the reference generator may be connected to the RA2/AN2/CV available on the PIC16F88 device only). This can be used as a simple D/A function by the user if a very high- impedance load is used. The primary purpose of this values and has function is to provide a test path for testing the reference generator function ...

Page 130

... V DD CVREN 8R (1) RA2/AN2/ pin REF REF CVROE CV REF Input to Comparator Note available on the PIC16F88 device only. REF TABLE 14-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Address Name Bit 7 Bit 6 9Dh CVRCON CVREN CVROE 9Ch CMCON C2OUT C1OUT Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference. ...

Page 131

... Reset while the power supply stabilizes and is enabled or disabled using a configuration bit. With these two timers on-chip, most applications need no external Reset circuitry.  2005 Microchip Technology Inc. PIC16F87/88 Sleep mode is designed to offer a very low-current Power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer wake-up or through an interrupt ...

Page 132

... LP oscillator Legend Readable bit -n = Value at POR DS30487C-page 130 R/P-1 R/P-1 R/P-1 CPD LVP BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/P-1 R/P-1 R/P-1 R/P-1 bit Bit is unknown  2005 Microchip Technology Inc. ...

Page 133

... IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled bit 0 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Legend Readable bit -n = Value at POR  2005 Microchip Technology Inc. U-1 U-1 U-1 U-1 U-1 — — — — ...

Page 134

... This delay runs in parallel with any other timers. See Table 15-4 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 15-  2005 Microchip Technology Inc. Chip_Reset Enable PWRT Enable OST ...

Page 135

... V is specified. See Section 18.0 “Electrical DD Characteristics” for details.  2005 Microchip Technology Inc. When the device starts normal operation (exits the Reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met ...

Page 136

... Illegal set on POR 0 Brown-out Reset 1 WDT Reset 1 WDT Wake-up 0 MCLR Reset during Normal Operation u MCLR Reset during Sleep or Interrupt Wake-up from Sleep 0 Wake-up from Sleep PWRTE = 1 1024 • T 1024 • T OSC OSC (1) (1) 5-10 s 5-10 s (1) — 5-10 s  2005 Microchip Technology Inc. ...

Page 137

... Brown-out Reset W xxxx xxxx INDF TMR0 xxxx xxxx PCL 0000h STATUS 0001 1xxx FSR xxxx xxxx PORTA (PIC16F87) xxxx 0000 PORTA (PIC16F88) xxx0 0000 PORTB (PIC16F87) xxxx xxxx PORTB (PIC16F87) 00xx xxxx PCLATH ---0 0000 INTCON 0000 000x PIR1 -000 0000 PIR2 00-0 ---- ...

Page 138

... Microchip Technology Inc. ...

Page 139

... MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 15-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED NETWORK): CASE MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET  2005 Microchip Technology Inc. PIC16F87/88 T PWRT T OST T PWRT T OST T PWRT T OST THROUGH ...

Page 140

... Q cycle. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit, PEIE bit or the GIE bit.  2005 Microchip Technology Inc. ...

Page 141

... EEIE OSFIF OSFIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE CMIF CMIE  2005 Microchip Technology Inc. PIC16F87/88 Wake-up (if in Sleep mode) TMR0IF TMR0IE INT0IF INT0IE RBIF RBIE PEIE GIE Interrupt to CPU DS30487C-page 139 ...

Page 142

... Since the upper 16 bytes of each bank are common in the PIC16F87/88 devices, temporary holding registers W_TEMP, STATUS_TEMP and should be placed in here. These 16 locations don’t require banking and therefore, make it easier for context save and restore. The same code shown in Example 15-1 can be used.  2005 Microchip Technology Inc. PCLATH_TEMP ...

Page 143

... Oscillator fail detected Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, ECIO Exit Sleep + System Clock = XT, HS, LP  2005 Microchip Technology Inc. A new prescaler has been added to the path between the internal RC and the multiplexors used to select the path for the WDT. This prescaler is 16 bits and can be ...

Page 144

... Bit is cleared Bit 6 Bit 5 Bit 4 Bit 3 INTEDG T0CS T0SE PSA BOREN MCLRE FOSC2 PWRTEN — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN R/W-0 R/W-0 R/W-0 (1) bit 0 ( Bit is unknown Bit 2 Bit 1 Bit 0 PS2 PS1 PS0 WDTEN FOSC1 FOSC0  2005 Microchip Technology Inc. ...

Page 145

... Sleep OSTS Program PC Counter  2005 Microchip Technology Inc. Checking the state of the OSTS bit will confirm whether the primary clock configuration is engaged. If not, the OSTS bit will remain clear. When the device is auto-configured in INTRC mode following a POR or wake-up from Sleep, the rules for entering other oscillator modes still apply, meaning the SCS< ...

Page 146

... T1OSC, INTRC or none (Sleep mode). How- ever, the FSCM will continue to monitor the system clock. If the secondary clock fails, the device will immediately switch to the internal oscillator clock. If OSFIE is set, an interrupt will be generated. Oscillator Failure CM Test Failure Detected CM Test  2005 Microchip Technology Inc. ...

Page 147

... Monitoring the OSTS bit will determine if the crystal is operating. The user should not enter Sleep mode without handling the fail-safe condition first.  2005 Microchip Technology Inc. PIC16F87/88 2. CONDITIONS: After a POR (Power-on Reset), the device is running in Two-Speed Start-up mode ...

Page 148

... To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. ( (2) T OST Interrupt Latency (Note 2) Processor in Sleep Inst( Dummy Cycle Inst( 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h)  2005 Microchip Technology Inc. ...

Page 149

... This also allows the most recent firmware or a custom firmware to be programmed.  2005 Microchip Technology Inc. For more information on serial programming, please refer to the “PIC16F87/88 Flash Memory Programming Specification” (DS39607). ...

Page 150

... PIC16F87/88 devices will enter Programming mode. 5: LVP mode is enabled by default on all devices shipped from Microchip. It can be disabled by clearing the LVP bit in the CONFIG1 register. 6: Disabling LVP will provide maximum compatibility devices.  2005 Microchip Technology Inc. to the IHH ICSP mode to other PIC16CXXX ...

Page 151

... A read operation is performed on a register even if the instruction writes to that register.  2005 Microchip Technology Inc. For example, a “CLRF PORTB” instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unintended result that the condition that sets the RBIF flag would be cleared ...

Page 152

... PD TO 0000 0110 0100 , 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO PD 0000 0110 0011 , C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk ® Mid-Range MCU  2005 Microchip Technology Inc. ...

Page 153

... Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register.  2005 Microchip Technology Inc. ANDWF k Syntax: Operands: Operation: Status Affected: Description: BCF Syntax: f,d Operands: Operation: ...

Page 154

... W register is cleared. Zero bit (Z) is set. Clear Watchdog Timer [ label ] CLRWDT None 00h WDT, 0 WDT prescaler TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.  2005 Microchip Technology Inc. ...

Page 155

... If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making instruction. CY  2005 Microchip Technology Inc. PIC16F87/88 GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands: 0 ...

Page 156

... The eight-bit literal ‘k’ is loaded into W register. The don’t cares will assemble as ‘0’s. Move label ] MOVWF 127 (W) (f) None Move data from W register to register ‘f’. No Operation [ label ] NOP None No operation None No operation.  2005 Microchip Technology Inc. ...

Page 157

... TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction.  2005 Microchip Technology Inc. PIC16F87/88 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands: 0 ...

Page 158

... XORWF Operands 127 d [0,1] Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ the result is stored in the W register. If ‘d’ the result is stored back in register ‘f’.  2005 Microchip Technology Inc. f,d ...

Page 159

... Developer Kits - CAN ® - PowerSmart Developer Kits - Analog  2005 Microchip Technology Inc. PIC16F87/88 17.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...

Page 160

... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines.  2005 Microchip Technology Inc. software ...

Page 161

... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.  2005 Microchip Technology Inc. PIC16F87/88 17.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...

Page 162

... H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a proto- typing area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User’s Guide.  2005 Microchip Technology Inc. ...

Page 163

... Tricks for 8-pin Flash PIC Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.  2005 Microchip Technology Inc. 17.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...

Page 164

... PIC16F87/88 NOTES: DS30487C-page 162  2005 Microchip Technology Inc. ...

Page 165

... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2005 Microchip Technology Inc. (except V and MCLR) ................................................... -0. (Note 2) ...

Page 166

... PIC16LF87/88 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (12 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN Note 2: F has a maximum frequency of 10 MHz. MAX DS30487C-page 164 16 MHz Frequency 4 MHz 10 MHz Frequency – 2.5V MHz DDAPPMIN ® 20 MHz device in the application.  2005 Microchip Technology Inc. ...

Page 167

... Note 1: This is the limit to which V can be lowered in Sleep mode, or during a device Reset, without losing RAM data When BOR is enabled, the device will operate correctly until the V  2005 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40° ...

Page 168

... V DD 1.7 A +85°C 1.0 A -40°C 1.0 A +25° 5.0 A +85° +125°C is not included. The current through the resistor can be estimated EXT (mA) with EXT Conditions = 2.0V = 3. and all features that add delta  2005 Microchip Technology Inc. ...

Page 169

... OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V MCLR = V ; WDT enabled/disabled as specified For RC oscillator configurations, current through R by the formula /2R DD EXT  2005 Microchip Technology Inc. -40°C T +85°C for industrial A -40°C T +85°C for industrial A -40°C T +125° ...

Page 170

... A +85°C 1.5 mA +125°C is not included. The current through the resistor can be estimated EXT (mA) with EXT Conditions = 2. OSC Z (3) (RC Oscillator) = 5.0V = 2. MHz OSC (3) (RC Oscillator and all features that add delta  2005 Microchip Technology Inc. ...

Page 171

... OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V MCLR = V ; WDT enabled/disabled as specified For RC oscillator configurations, current through R by the formula /2R DD EXT  2005 Microchip Technology Inc. -40°C T +85°C for industrial A -40°C T +85°C for industrial A -40°C T +125° ...

Page 172

... The current through the resistor can be estimated EXT (mA) with EXT Conditions = 2. 31.25 kHz OSC = 3.0V (RC_RUN mode, Internal RC Oscillator) = 5. MHz OSC = 3.0V (RC_RUN mode, Internal RC Oscillator and all features that add delta  2005 Microchip Technology Inc. ...

Page 173

... OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V MCLR = V ; WDT enabled/disabled as specified For RC oscillator configurations, current through R by the formula /2R DD EXT  2005 Microchip Technology Inc. -40°C T +85°C for industrial A -40°C T +85°C for industrial A -40°C T +125° ...

Page 174

... The current through the resistor can be estimated EXT (mA) with EXT Conditions = 3. MHz OSC (RC_RUN mode, Internal RC Oscillator) = 5. kHz OSC = 3.0V (SEC_RUN mode, Timer1 as clock and all features that add delta  2005 Microchip Technology Inc. ...

Page 175

... OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V MCLR = V ; WDT enabled/disabled as specified For RC oscillator configurations, current through R by the formula /2R DD EXT  2005 Microchip Technology Inc. -40°C T +85°C for industrial A -40°C T +85°C for industrial A -40°C T +125° ...

Page 176

... Conditions (1) +25°C -10°C to +85° 2.7-3.3V DD -40°C to +85°C 25°C -10°C to +85° 4.5-5.5V DD -40°C to +85°C -40°C to +125° 4.5-5.5V DD -40°C to +85° 2.7-3.3V DD -40°C to +85° 4.5-5.5V DD  2005 Microchip Technology Inc. ...

Page 177

... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.  2005 Microchip Technology Inc. PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) Standard Operating Conditions (unless otherwise stated) ...

Page 178

... OSC1 pF pF E/W - E/W + +125 C V Using EECON to read/write min. operating voltage MIN 8 ms E/W - E/W + +125 Using EECON to read/write min. operating voltage MIN  2005 Microchip Technology Inc. ...

Page 179

... T (1)* SET Settling Time * These parameters are characterized but not tested. Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’.  2005 Microchip Technology Inc. < +85°C, unless otherwise stated A Min Typ — ±5.0 0 — ...

Page 180

... C specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z High-impedance High High Low Low SU Setup STO Stop condition Load Condition Pin  2005 Microchip Technology Inc. ...

Page 181

... All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.  2005 Microchip Technology Inc ...

Page 182

... (Note 1) CY — — ns (Note 1) — — ns (Note 1) 100 255 ns — — ns — — ns — — — 145 — 145 ns — — ns — — ns  2005 Microchip Technology Inc. ...

Page 183

... Brown-out Reset Pulse Width BOR * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2005 Microchip Technology Inc. PIC16F87/ BOR ...

Page 184

... CY N PIC16F87/88 60 — — PIC16LF87/88 100 — — DC — 32.768 2 T — OSC  2005 Microchip Technology Inc. 48 Units Conditions ns Must also meet parameter Must also meet parameter prescale value (2, 4, ..., 256) ns Must also meet parameter 47 ...

Page 185

... TccF CCP1 Output Fall Time * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2005 Microchip Technology Inc Min 0 ...

Page 186

... SCK (CKP = 1) SDO MSb SDI MSb In 74 Note: Refer to Figure 18-3 for load conditions. DS30487C-page 184 MSb Bit 75, 76 Bit Bit 75, 76 Bit LSb LSb LSb LSb  2005 Microchip Technology Inc. ...

Page 187

... SPI™ SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI MSb In 74 Note: Refer to Figure 18-3 for load conditions.  2005 Microchip Technology Inc Bit MSb 75, 76 Bit LSb Bit 75, 76 Bit LSb In ...

Page 188

... Stop Condition  2005 Microchip Technology Inc. ...

Page 189

... C™ BUS DATA TIMING 103 SCL 90 91 SDA In 109 SDA Out Note: Refer to Figure 18-3 for load conditions.  2005 Microchip Technology Inc. Min Typ Max Units 100 kHz mode 4700 — — ns 400 kHz mode 600 — — 100 kHz mode 4000 — ...

Page 190

... Time the bus must be free before a new transmission — s can start 400 bus system, but = 1000 + 250 = 1250 ns (according to the  2005 Microchip Technology Inc. ...

Page 191

... SYNC RCV (MASTER & SLAVE) Data Setup before CK 126 TckL2dtl Data Hold after CK † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested.  2005 Microchip Technology Inc. 121 Characteristic Min PIC16F87/88 — PIC16LF87/88 — ...

Page 192

... AIN REF (Note 4) A Average current consumption when A (Note 1) A During V acquisition. AIN Based on differential of V HOLD charge C , AIN HOLD see Section 12.1 “A/D Acquisition Requirements”. A During A/D conversion cycle  2005 Microchip Technology Inc. ...

Page 193

... Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note 1: ADRES registers may be read on the following T 2: See Section 12.1 “A/D Acquisition Requirements” for minimum conditions.  2005 Microchip Technology Inc. (1) 131 130 OLD_DATA Sampling Stopped is added before the A/D clock starts ...

Page 194

... PIC16F87/88 NOTES: DS30487C-page 192  2005 Microchip Technology Inc. ...

Page 195

... Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 7 Minimum: mean – 3 (-40°C to +125°  2005 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC (MHz) OSC vs. F OVER V (HS MODE) OSC ...

Page 196

... DS30487C-page 194 vs. F OVER V (XT MODE) OSC DD 1500 2000 2500 F (MHz) OSC vs. F OVER V (XT MODE) OSC DD 1500 2000 2500 F (MHz) OSC 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3000 3500 4000 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 3000 3500 4000  2005 Microchip Technology Inc. ...

Page 197

... Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 100  2005 Microchip Technology Inc. vs. F OVER V (LP MODE) OSC (kHz) OSC vs. F OVER V (LP MODE) ...

Page 198

... Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 DS30487C-page 196 vs - +125 C, 1 MHz TO 8 MHz DD 3.0 4.0 5.0 F (MHz) OSC vs - +125 C, 1 MHz TO 8 MHz DD 3.0 4.0 5.0 F (MHz) OSC 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 6.0 7.0 8.0 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 6.0 7.0 8.0  2005 Microchip Technology Inc. ...

Page 199

... FIGURE 19-10 +125 C (SLEEP MODE, ALL PERIPHERALS DISABLED 100 10 1 0.1 0.01 0.001 2.0 2.5  2005 Microchip Technology Inc. Max (+70°C) 3.0 3.5 4.0 Vdd(V) Max (125°C) Max (85°C) Typ (25°C) Typical: Maximum: mean + 3 (-40°C to +125°C) Minimum: 3.0 3.5 4.0 V (V) DD PIC16F87/88 Typ (+25°C) 4 ...

Page 200

... Operation above 4 MHz is not recommended 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 FIGURE 19-12: AVERAGE F OSC (RC MODE 100 pF, +25 C) 2.5 2.0 1.5 1.0 0.5 0.0 2.0 2.5 DS30487C-page 198 vs. V FOR VARIOUS VALUES OF R (RC MODE pF, + 3.5 4.0 V (V) DD vs. V FOR VARIOUS VALUES 3.0 3.5 4.0 V (V) DD 5.1 kOhm 10 kOhm 100 kOhm 4.5 5.0 5.5 3.3 kOhm 5.1 kOhm 10 kOhm 100 kOhm 4.5 5.0 5.5  2005 Microchip Technology Inc. ...

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