74LV125PW,118 NXP Semiconductors, 74LV125PW,118 Datasheet - Page 6
![IC BUFF DVR TRI-ST QUAD 14TSSOP](/photos/6/58/65814/568-14-tssop_sot402-1_sml.jpg)
74LV125PW,118
Manufacturer Part Number
74LV125PW,118
Description
IC BUFF DVR TRI-ST QUAD 14TSSOP
Manufacturer
NXP Semiconductors
Series
74LVr
Datasheet
1.74LV125N112.pdf
(15 pages)
Specifications of 74LV125PW,118
Package / Case
14-TSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
16mA, 16mA
Voltage - Supply
1 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LV
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 16 mA
Input Bias Current (max)
160 uA
Low Level Output Current
16 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
55 ns (Typ) @ 1.2 V or 19 ns (Typ) @ 2 V or 14 ns (Typ) @ 2.7 V or 10 ns (Typ) @ 3.3 V
Number Of Lines (input / Output)
4 / 4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LV125PW-T
74LV125PW-T
935174350118
74LV125PW-T
935174350118
NXP Semiconductors
Table 7.
Voltages are referenced to GND (ground = 0 V). For test circuit see
[1]
[2]
[3]
[4]
11. Waveforms
74LV125_3
Product data sheet
Symbol Parameter
t
C
dis
Fig 6.
PD
All typical values are measured at T
t
t
t
Typical values are measured at nominal supply voltage (V
C
P
f
C
V
N = number of inputs switching
pd
en
dis
I
(C
D
CC
PD
= input frequency in MHz, f
L
is the same as t
is the same as t
= output load capacitance in pF
is the same as t
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts
disable time
power dissipation
capacitance
Measurement points are given in
V
The input (nA) to output (nY) propagation delays
PD
V
OL
Dynamic characteristics
CC
2
and V
V
CC
f
o
2
) = sum of the outputs.
OH
PLH
PZL
f
PLZ
i
are typical voltage output levels that occur with the output load.
and t
N + (C
and t
and t
PZH
PHL
PHZ
o
Conditions
nOE to nY; see
V
V
V
V
V
C
V
= output frequency in MHz
L
CC
CC
CC
CC
CC
I
L
.
.
.
= GND to V
= 50 pF; f
V
= 1.2 V
= 2.0 V
= 2.7 V
= 3.0 V to 3.6 V
= 4.5 V to 5.5 V
CC
amb
nY output
nA input
2
…continued
= 25 C.
Table
f
o
) where:
i
= 1 MHz;
CC
8.
GND
V
V
Figure 7
OH
; V
OL
V
I
CC
Rev. 03 — 7 April 2009
= 3.3 V
CC
D
V
= 3.3 V).
in W).
M
V
M
t
PHL
[2]
[3]
[4]
Figure
Min
-
-
-
-
-
-
40 C to +85 C
8.
Typ
65
24
18
14
22
-
mna230
[1]
t
PLH
Max
Quad buffer/line driver; 3-state
32
24
20
17
-
-
Min
40 C to +125 C
-
-
-
-
-
-
© NXP B.V. 2009. All rights reserved.
74LV125
Max
39
29
24
21
-
-
6 of 15
Unit
ns
ns
ns
ns
ns
pF