MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet - Page 9

• Manufacturer Part Number: MSAN-141
• Description: Implementation Details of the MT8930B-31B S-T Interface
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
All the time intervals mentioned above are inherent
in the SNIC silicon. The response time to the INFO
signals are relevant to the detection algorithms for
each signals. (These algorithms are detailed in the
following section.) The timer (timer 2) implemented
on the SNIC, (to avoid unintentional reactivation of
the NT) has been set to 32 ms which is well in the
range of 25 to 100 ms specified above.
2.3.3 INFO Detection Algorithms
The activation times for the TE and the NT, are
determined by the detection algorithms for the
INFO0 through INFO4 signals. The detection
scheme used for the INFO signals will identify the
worst case detection time under no-fault conditions.
The MT8930B/31B uses a combination of an energy
detection circuit in conjunction with a timer in order
to detect the INFO1 signal. The detection of INFO2
relies on the convergence of the PLL as well as the
framer of the MT8930B/31B. Once activity occurs on
the line, the PLL will train the clocks to the correct
frequency before sampling the received data. The
INFO2 signal is detected upon the occurrence of a
synchronized state with the AR bit set to binary”0”.
Therefore, under normal conditions (no errors), the
worst case synchronization time is two frames
following the convergence of the PLL.
The NT detects the reception of INFO3 upon the
synchronization of the incoming signal. Since the
PLL need not be trained, the detection of INFO3 is
directly related to the synchronization algorithm.
The INFO4 signal is identified by the status of the A-
bit. If the TE is synchronized to the received line
signal, it will identify INFO4 on the first occurrence of
the A-bit = 1
of the A-bit will occur within two ST-BUS frames or
250 s.
The SNIC provides an internal signal labelled “Bus
Activity“. This signal will go high when three zeros
are received in a time period equivalent to 48 bits or
250 s. Receiving 128 consecutive ONEs resets this
signal. This scheme allows the detection of INFO0 in
about 667
reflects the binary value of this signal.
2.4
In a multidrop configuration, a systematic approach
is required to allow competing TEs access to the
single 16 kbit/s D-channel. A layer 1 priority scheme
has been implemented to allocate terminal priority as
well as provide contention resolution.
D-Channel Access
B
s. Bit 7 of the Mode Status Register
. Therefore, the detection and reporting
A TE gains access to the D-channel when it reaches
its priority count. This is accomplished by monitoring
the received D-echo channel (E-bit) transmitted from
the NT and counting the number of consecutive
binary ones. Any zero received on the E-bit will
restart the counting process. The priority mechanism
is based on this counting process, such that, a TE
can only start transmitting once the counter is equal
to, or exceeds the value of its priority class.
Any TE which is not using the on-chip HDLC, (using
ST-BUS D-Channel) must request access to the D-
channel by raising the DReq bit (B3 of the TE mode
C-channel Control Register). The user must wait
until the D-channel acknowledgment bit (Dack) (B0
of the TE mode C-channel Status Register) is
received before forwarding the packet. If the TE fails
to respond to the Dack within an eight bit interval,
access to the D-channel may be lost as the priority
count on another TE may be attained.
The priority mechanism circuitry is activated once
the HDLC transmitter is enabled and data is written
to the TxFIFO.
2.4.1 Priority Classes
Using the counting algorithm mentioned above, the
MT8930B/31B can establish four levels of priority.
These priority levels are split into two classes, which
are subdivided into two levels (refer to Table 4). Only
the class of priority is accessible to the user through
B4 of the TE mode C-channel control register.
The level of priority is strictly internal to the device
and cannot be accessed by the user. In a priority
class, the level of priority is changed from high to low
when the TE has successfully completed its
transmission. The level of priority is reinstated only
after the priority count for the respective TE has
been attained.
2.4.2 Collision Detection
The D-echo channel is also used to detect
contention on the D-channel. The TEs which are
trying to access the D-channel will monitor the E-bit
Class
High
High
Low
Low
Table 4. Priority Classes
Level
High
High
Low
Low
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