STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 20

• Manufacturer Part Number: STG3005A2S
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

RIVA128ZX
Figure 10. 2X Basic write no delay
Figure 10 is a basic write transaction that transfers data at the 2X rate. There is no difference in the control
signals from AGP 1x mode - only more data is moved. The normal control signals determine when data is
valid.
Figure 11. QuadWord writes back to back - no delays
Figure 11 illustrates multiple 8 byte write operations compared with the single transfer shown in Figure 10.
When the transactions are short, the arbiter is required to give grants on every clock or the AD bus will not
be totally utilized. In this example a new write is started on each rising clock edge except clock 7, because
the arbiter deasserted PCIGNT# on clock 6. Since a new transaction is started on each CLK, PCIIRDY#
is only deasserted on clock 7.
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AGPADSTBx
AGPADSTBx
PCIAD[31:0]
PCIAD[31:0
AGPST[2:0]
AGPST[2:0]
PCITRDY#
PCITRDY#
PCIIRDY#
PCIIRDY#
PCIREQ#
PCIGNT#
PCICBE#
PCIGNT#
PCICBE#
PCICLK
PCICLK
]
xx
1
1
xx
xxx
01x
2
2
xxx
01x
W3
BE BE
3
3
+1 W4
01x
01x
BE BE
4
4
+1
W1 +1
BE BE
01x
xxx
W5
BE
128-BIT 3D MULTIMEDIA ACCELERATOR
5
5
BE
+1
BE BE BE
+2 +3 +4
xxx
xxx
W6
BE BE
6
6
+1
01x
xxx
7
7
BE BE BE
+5 +6 +7
01x
W7
BE
xxx
8
8
BE
+1
xxx
W8
BE BE
xxx
9
9
+1
x