STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 37

• Manufacturer Part Number: STG3005A2S
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
6.4
Separate clock signals FBCLK0 and FBCLK1 are provided for each bank of memory to give reduced
clock skew and loading. Additionally there is a clock feedback loop between FBCLK2 and FBCLKFB.
It is recommended that long traces are used without tunable components. If the layout includes provision
for expansion to 8MBytes, the clock path to the 4MByte parts should be at the end of the trace, and the
clock path to the 8MByte expansion located between the RIVA128ZX and the 4MByte parts as shown in
Figure 32. FBCLK2 and FBCLKFB should be shorted together as close to the package as possible.
Figure 32. Recommended memory clock layout
6.5
Figure 33. SDRAM/SGRAM I/O timing diagram
Table 10. SDRAM/SGRAM I/O timing parameters
Symbol
t
t
t
t
t
t
CK
CH
CL
AS
AH
DS
LAYOUT OF FRAMEBUFFER CLOCK SIGNALS
FRAMEBUFFER INTERFACE TIMING SPECIFICATION
FBA[10:0], FBD[63:0]
CLK period
CLK high time
CLK low time
Address setup time
Address hold time
Write data setup time
FBD[63:0]
FBCLKx
Parameter
RIVA128ZX
FBCLKFB
FBCLK2
FBCLK0
FBCLK1
t
AS
-10
3.5
3.5
10
3
1
3
, t
t
LZ
t
DS
CH
t
Min.
AH
t
, t
AC
t
DH
CK
-12
4.5
4.5
to 8MBytes
12
Expansion
4
1
4
Bank 1
512K
512K
x32
x32
t
t
t
CL
-10
-
-
-
-
-
-
Max.
Bank 0
512K
512K
t
OH
x32
x32
-12
-
-
-
Unit
ns
ns
ns
ns
ns
ns
RIVA128ZX
Notes
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