STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 32
STG3000X-RIVA128
Manufacturer Part Number
STG3000X-RIVA128
Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Manufacturer
STMicroelectronics
Datasheet
1.STG3000X-RIVA128.pdf
(77 pages)
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RIVA 128
Figure 26. SGRAM random read accesses within a page, read latency of two
NOTE
Figure 27. SGRAM random read accesses within a page, read latency of three
NOTE
32/77
Symbol
t
t
t
t
t
t
t
t
CL
AS
AH
DS
DH
OH
AC
LZ
1
1
Covers either successive reads to the active row in a given bank, or to the active rows in different banks. DQMs are all
active (LOW).
Covers either successive reads to the active row in a given bank, or to the active row s in different banks.FBDQ M is all
active (LOW).
Command
Command
FBD[63:0]
FBD[63:0]
FBA[9:0]
FBA[9:0]
FBCLKx
FBCLKx
CLK low time
Address setup time
Address hold time
Write data setup time
Write data hold time
Read data hold time
Read data access time
Data out low impedance time
Parameter
bank, col n bank, col a bank, col x bank, col m
bank, col n bank, col a bank, col x bank, col m
read
read
read
read
-10
3.5
3
1
3
1
3
9
0
read
Min.
read
data n
-12
4.5
1
4
1
3
9
4
0
128-BIT 3D MULTIMEDIA ACCELERATOR
read
data n
read
-10
data a
-
-
-
-
-
-
-
-
nop
data a
Max.
nop
-12
-
data x
nop
data x
1
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
nop
nop
data m
data m
Notes
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