CD4025BMS Intersil Corporation, CD4025BMS Datasheet

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CD4025BMS

Manufacturer Part Number
CD4025BMS
Description
Rad-hard Cmos Nor Gate
Manufacturer
Intersil Corporation
Datasheet
November 1994
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• High-Voltage Types (20V Rating)
• Propagation Delay Time = 60ns (typ.) at CL = 50pF,
• Buffered Inputs and Outputs
• Standard Symmetrical Output Characteristics
• 100% Tested for Maximum Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1 A at 18V Over Full Pack-
• Noise Margin (Over Full Package Temperature Range):
• Meets All Requirements of JEDEC Tentative Stan-
Description
CD4000BMS
CD4001BMS
CD4002BMS
CD4025BMS
CD4000BMS,
CD4025BMS NOR gates provide the system designer with
direct implementation of the NOR function and supplement
the existing family of CMOS gates. All inputs and outputs are
buffered.
The CD4000BMS, CD4001BMS, CD4002BMS and the
CD4025BMS is supplied in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
VDD = 10V
age-Temperature Range; 100nA at 18V and +25
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Device’s
- Dual 3 Plus Inverter
- Quad 2 Input
- Dual 4 Input
- Triple 3 Input
CD4001BMS,
CD4000B CD4001B CD4002B CD4025B
H3W
H4X
H1B
H3W
H4Q
H1B
CD4002BMS,
H3W
H4Q
H1B
CD4000BMS, CD4001BMS
CD4002BMS, CD4025BMS
o
H3W
H4Q
H1B
C
and
7-649
Pinouts
J = A + B + C + D
H = A + B + C
K = D + E + F
K = C + D
J = A + B
VSS
VSS
VSS
VSS
NC
NC
NC
A
B
C
A
B
C
D
A
B
C
D
A
B
D
E
F
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1
2
3
4
5
6
7
CD4000BMS
CD4001BMS
CD4002BMS
CD4025BMS
TOP VIEW
TOP VIEW
TOP VIEW
TOP VIEW
CMOS NOR Gate
14
13
12
10
14
13
12
10
14
13
12
10
14
13
12
10
11
11
11
11
9
8
9
8
9
8
9
8
VDD
F
E
D
K = D + E + F
L = G
G
VDD
H
G
M = G + H
L = E + F
F
E
VDD
K = E + F + G + H
H
G
F
E
NC
VDD
G
H
I
L = G + H + I
J = A + B + C
C
NC = NO CONNECTION
NC = NO CONNECTION
NC = NO CONNECTION
NC = NO CONNECTION
File Number
3289

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CD4025BMS Summary of contents

Page 1

... CD4025BMS NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4000BMS, CD4001BMS, CD4002BMS and the CD4025BMS is supplied in these 14 lead outline packages: CD4000B CD4001B CD4002B CD4025B Braze Seal DIP H4X H4Q ...

Page 2

... CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS Functional Diagrams VSS CD4000BMS VSS 7 CD4002BMS A 14 VDD ...

Page 3

... Specifications CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input Operating Temperature Range . . . . . . . . . . . . . . . . -55 Package Types Storage Temperature Range (TSTG -65 Lead Temperature (During Soldering +265 At Distance 1/16 1/32 Inch (1 ...

Page 4

... Specifications CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) Propagation Delay TPHL VDD = 5V, VIN = VDD or GND TPLH Transition Time TTHL VDD = 5V, VIN = VDD or GND TTLH NOTES 50pF 200K, Input TR, TF < 20ns -55 C and +125 C limits guaranteed, 100% testing being implemented ...

Page 5

... Specifications CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Input Capacitance CIN Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics 50pF 200K, Input TR, TF < ...

Page 6

... Specifications CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS MIL-STD-883 CONFORMANCE GROUPS METHOD Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN PART NUMBER CD4000BMS Static Burn- Note 1 Static Burn- Note 1 Dynamic Burn Note 1 ...

Page 7

... Specifications CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS Schematic and Logic Diagrams 14 VDD 6(10 (12 (11) n INVERTER AND GATES (NUMBERS IN 4* PARENTHESES ARE n TERMINAL NUMBERS (13) FOR SECOND GATE) 7 VSS 5(12) 3(11) LOGIC DIAGRAM 4(13) 8 CD4000BMS ...

Page 8

... CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS Typical Performance Characteristics AMBIENT TEMPERATURE ( +25 A SUPPLY VOLTAGE (VDD) = 15V 15 10V INPUT VOLTAGE (VI) (V) FIGURE 1. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS AMBIENT TEMPERATURE ( + GATE-TO-SOURCE VOLTAGE (VGS) = 15V 10V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3 ...

Page 9

... CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS Typical Performance Characteristics AMBIENT TEMPERATURE ( +25 A 200 SUPPLY VOLTAGE (VDD 150 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME vs LOAD CAPACITANCE Chip Dimensions and Pad Layouts CD4000BMS CD4002BMS Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10 ...

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