CD4024BMS Intersil Corporation, CD4024BMS Datasheet

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CD4024BMS

Manufacturer Part Number
CD4024BMS
Description
Rad-hard Cmos Ripple-carry Binary Counter/dividers
Manufacturer
Intersil Corporation
Datasheet
October 1996
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• High Voltage Types (20V Rating)
• Medium Speed Operation
• Fully Static Operation
• Buffered Inputs and Outputs
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• Common Reset
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1 a at 18V Over Full Pack-
• Noise Margin (Over Full Package Temperature Range):
• Meets All Requirements of JEDEC Tentative Standard
Applications
• Control Counters
• Timers
• Frequency Dividers
• Time-Delay Circuits
Description
CD4020BMS - 14 Stage
CD4024BMS - 7 Stage
CD4040BMS - 12 Stage
CD4020BMS, CD4024BMS, and CD4040BMS are ripple-
carry binary counters. All counter stages are master-slave
flip-flops. The state of a counter advances one count on the
negative transition of each input pulse; a high level on the
RESET line resets the counter to its all zeros state. Schmitt
trigger action on the input-pulse line permits unlimited rise
and fall times. All inputs and outputs are buffered.
The CD4020BMS, CD4024BMS and the CD4040BMS is
supplied in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
age-Temperature Range;
- 100nA at 18V and 25
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
No. 13B, “Standard Specifications For Description Of
‘B’ Series CMOS Devices”
CD4020B
H4W
H6W
H1F
o
C
CD4024B
H3W
H4Q
H1B
CD4020BMS, CD4024BMS,
CD4040B
H6W
H4X
H1F
7-359
Pinouts
NC = NO CONNECTION
RESET
VSS
VSS
Q12
Q13
Q14
VSS
Q12
Q6
Q5
Q7
Q4
Q6
Q5
Q7
Q4
Q3
Q2
Q7
Q6
Q5
Q4
CMOS Ripple-Carry Binary
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
CD4040BMS
CD4020BMS
CD4024BMS
CD4040BMS
TOP VIEW
TOP VIEW
TOP VIEW
Counter/Dividers
16
15
14
13
12
11
10
14
13
12
10
11
16
15
14
13
12
11
10
9
8
9
9
VDD
Q11
Q10
Q8
Q9
RESET
Q1
VDD
Q11
Q10
Q8
Q9
R
Q1
VDD
NC
Q1
Q2
NC
Q3
NC
File Number
3300.1

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CD4024BMS Summary of contents

Page 1

... RESET line resets the counter to its all zeros state. Schmitt trigger action on the input-pulse line permits unlimited rise and fall times. All inputs and outputs are buffered. The CD4020BMS, CD4024BMS and the CD4040BMS is supplied in these 14 lead outline packages: CD4020B CD4024B ...

Page 2

... Specifications CD4020BMS, CD4024BMS, CD4040BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input Operating Temperature Range . . . . . . . . . . . . . . . . -55 Package Types Storage Temperature Range (TSTG -65 Lead Temperature (During Soldering +265 At Distance 1/16 1/32 Inch (1 ...

Page 3

... Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND TPLH1 Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND TPLH2 Propagation Delay TPLH3 VDD = 5V, VIN = VDD or GND ...

Page 4

... Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V Propagation Delay TPHL1 VDD = 10V Input To Q1 TPLH1 VDD = 15V ...

Page 5

... Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL NOTES: 1. All voltages referenced to device GND 50pF 200K, Input TR, TF < 20ns. TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) ...

Page 6

... Specifications CD4020BMS, CD4024BMS, CD4040BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION OPEN GROUND Static Burn- Note 1 Dynamic Burn Note 1 Irradiation Note 2 PART NUMBER CD4040BMS Static Burn- Note 1 Static Burn- ...

Page 7

... FIGURE 1. LOGIC DIAGRAM FOR CD4020BMS Ø1 Q1 Ø2 Q2 FF1 FF2 Ø1 Q1 Ø FIGURE 2. LOGIC DIAGRAM FOR CD4024BMS Ø1 Q1 Ø2 Q2 FF1 FF2 Ø1 Q1 Ø FIGURE 3. LOGIC DIAGRAM FOR CD4040BMS 7-365 Ø3 Q13 Ø14 Q14 FF14 Ø ...

Page 8

... CD4020BMS, CD4024BMS, CD4040BMS Typical Performance Characteristics AMBIENT TEMPERATURE ( + GATE-TO-SOURCE VOLTAGE (VGS) = 15V 10V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 o AMBIENT TEMPERATURE ( + GATE-TO-SOURCE VOLTAGE (VGS) = -5V ...

Page 9

... FIGURE 11. DETAIL OF TYPICAL FLIP-FLOP STAGES Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10 DIMENSIONS AND PAD LAYOUT FOR CD4024BMSH Å 14k Å , Silane 7-367 ...

Page 10

... CD4020BMS, CD4024BMS, CD4040BMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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