RS8234 Mindspeed Technologies, RS8234 Datasheet - Page 78
RS8234
Manufacturer Part Number
RS8234
Description
Atm Servicesar Plus With Xbr Traffic Management
Manufacturer
Mindspeed Technologies
Datasheet
1.RS8234.pdf
(401 pages)
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3.0 Host Interface
3.3 Write-Only Control and Status
3-12
Event Counter Mechanism
The event counter mechanism is enabled by setting INT_DELAY
(EN_STAT_CNT) to a logic high. An internal counter is implemented that counts
the number of status queue write events. The number of events before opening the
interrupt window is programmable via the INT_DELAY(STAT_CNT) field. The
window will be closed for STAT_CNT number of events. When the internal
counter has reached the value of STAT_CNT, the interrupt window will be
opened, which will allow the interrupt to propagate to the output pin. The counter
is reset when the status registers are read and the interrupt output goes inactive.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234
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