ADP3806 Analog Devices, Inc., ADP3806 Datasheet - Page 12

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ADP3806

Manufacturer Part Number
ADP3806
Description
High-frequency Switch Mode Li-ion Battery Charger
Manufacturer
Analog Devices, Inc.
Datasheet

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ADP3806
The oscillator frequency is set by the external capacitor at the
CT pin and the internal current source of 150 μA according to
the following formula:
A 180 pF capacitor sets the frequency to 250 kHz. The frequency
can also be synchronized to an external oscillator by applying a
square wave input on SYNC. The SYNC function is designed to
allow increases only in the oscillator frequency. The f
be no more than 20% higher than f
SYNC input is not important and can be anywhere between 5%
and 95%.
7 V BOOTSTRAP REGULATOR
The driver stage is powered by the internal 7 V bootstrap
regulator available at the BSTREG pin. Because the switching
currents are supplied by this regulator, decoupling must be
added. A 0.1 μF capacitor should be placed close to the
ADP3806, with the ground side connected close to the power
ground pin (PGND). This supply is not recommended for use
externally due to high switching noise.
BOOTSTRAPPED SYNCHRONOUS DRIVER
The PWM comparator controls the state of the synchronous
driver shown in Figure 20. A high output from the PWM
comparator forces DRVH on and DRVL off. The drivers have
an on resistance of approximately 6 Ω for fast rise and fall times
when driving external MOSFETs. Furthermore, the bootstrapped
drive allows an external NMOS transistor for the main switch
instead of a PMOS. An external boost diode should be connected
between BSTREG and BST, and a boost capacitor of 0.1 μF must
be added externally between BST and SW. The voltage between
BST and SW is typically 6.5 V.
The DRVL pin switches between BSTREG and PGND. The 7 V
output of BSTREG drives the external NMOS with high VGS to
lower the on resistance. PGND should be connected close to the
source pin of the external synchronous NMOS. When DRVL is
high, this turns on the lower NMOS and pulls the SW node to
ground. At this point, the boost capacitor is charged up through
the boost diode. When the PWM switches high, DRVL is turned
off and DRVH turns on. DRVH switches between BST and SW.
When DRVH is on, the SW pin is pulled up to the input supply
(typically 16 V), and BST rises above this voltage by
approximately 6.5 V.
Overlap protection is included in the driver to ensure that both
external MOSFETs are not on at the same time. When DRVH
turns off the upper MOSFET, the SW node goes low due to the
inductor current. The ADP3806 monitors the SW voltage, and
DRVL goes high to turn on the lower MOSFET when SW goes
below 1 V. When DRVL turns off, an internal timer adds a delay
of 50 ns before turning on DRVH.
f
OSC
=
2
2 .
×
150
Cr
μA
×
1
5 .
V
OSC
. The duty cycle of the
SYNC
should
Rev. C | Page 12 of 16
(3)
When the charge current is low, the DRVLSD comparator
signals the driver to turn off the low side MOSFET and DRVL is
held low. As shown in Figure 20, the DRVLSD comparator
looks at the output of AMP1. The DRVLSD threshold is set to
1.2 V, corresponding to 48 mV differential voltage between
the CS pins.
The driver stage monitors the voltage across the BST capacitor
with CMP3. When this voltage is less than 4 V, CMP3 forces a
minimum offtime of 200 ns. This ensures that the BST capacitor
is charged even during DRVLSD. However, because a minimum
off time is only forced when needed, the maximum duty cycle is
greater than 99%.
2.5 V PRECISION REFERENCE
The voltage at the BAT pin is compared to an internal precision,
low temperature drift reference of 2.5 V. The reference is available
externally at the REF pin. This pin should be bypassed with a
100 pF capacitor to the analog ground pin (AGND). The
reference can be used as a precision voltage externally. However,
the current draw should not be greater than 100 μA, and noisy,
switching type loads should not be connected.
6 V REGULATOR
The 6 V regulator supplies power to most of the analog circuitry
on the ADP3806. This regulator should be bypassed to AGND
with a 0.1 μF capacitor. This reference has a 3 mA source
capability to power external loads if needed.
LC
The ADP3806 provides a low current (LC) logic output to
signal when the current sense voltage (V
threshold and the battery voltage is greater than 95%. LC is an
open-drain output that is pulled low when V
threshold. When the low current threshold condition is reached,
LC is pulled high by an external resistor to REF or another
appropriate pull-up voltage. To determine when LC goes low, an
internal comparator senses when the current falls below 12.5%
of full scale (20 mV across the CS pins). The comparator has
hysteresis to prevent oscillation around the
trip point.
To prevent false triggering (such as during soft start), the
comparator is only enabled when the battery voltage is within
5% of its final voltage. As the battery charges up, the comparator
does not go low even if the current falls below 12.5% as long as
the battery voltage is below 95% of full scale. Once the battery
has risen above 95%, the comparator is enabled. This pin can be
used to indicate the end of the charge process.
SYSTEM CURRENT SENSE
An uncommitted differential amplifier is provided for
additional high side current sensing. This amplifier, AMP2,
has a fixed gain of 50 V/V from the SYS+ and SYS− pins to the
analog output at ISYS. ISYS has a 1 mA source capability to
CS
) is below a fixed
CS
is above the