78Q2132 TDK Corp., 78Q2132 Datasheet
78Q2132
Related parts for 78Q2132
78Q2132 Summary of contents
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... DESCRIPTION The 78Q2132 is a 1/10 Ethernet transceiver. This dual speed transceiver interfaces to a 1Mbps Home LAN and a 10BASE-T network. interface is fully Home Phoneline Networking Alliance (HomePNA) compliant extending POTS. The HomePNA interface includes the pulse encoder and decoder plus transmit and receive line interface filters ...
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... HomePNA/Ethernet Transceiver FUNCTIONAL DESCRIPTION GENERAL Supply Voltage The 78Q2132 can operate from either a single 3.3V ( 0.3V) or 5.0V ( 0.5V) power supply. The chip automatically adapts to the supply voltage used. No pin configuration is required. Power Management Chip power-down is activated by setting the PWRDN bit in the MII register (MR0.11) or pulling high the PWRDN pin ...
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... OPERATION 10BASE-T Transmit The 78Q2132 takes 4 bit parallel NRZ data via the MII interface and passes it through a parallel to serial converter. The data is then passed through a Manchester encoder and then on to the twisted pair pulse shaping circuitry and the twisted pair drive circuitry ...
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... T data rate as described in Clause 22 of the IEEE- 802.3 standard. The transmit clock, TX_CLK, provides the timing reference for the transfer of TX_EN, and TXD[3:0], signals from the MAC to the 78Q2132. TXD[3:0] is captured on the rising edge of TX_CLK when TX_EN is asserted. The receive clock, RX_CLK, provides the timing reference to transfer RX_DV, and RXD[3:0], signals from the 78Q2132 to the MAC ...
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... The Collision signal, CLSN, indicates a collision has been detected by the 2132 on the wiring network. MII/GPSI Selection The MII on the 78Q2132 is internally connected to the transmit and receive paths for either the 1M8 HomePNA or the 10BASE-T interface as described in Clause 22 of the IEEE 802.3 standard. The MII_EN pin selects the choice of interface or MII Enable bit MR16 ...
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... HomePNA/Ethernet Transceiver PIN DESCRIPTION LEGEND TYPE DESCRIPTION A Analog Pin O Digital Output S Supply MII (MEDIA INDEPENDENT INTERFACE)/ GPSI (GENERAL PURPOSE SERIAL INTERFACE) PIN 80-PIN 64-PIN TYPE TX_CLK 33 (GPSI & MII) TX_EN 34 (GPSI & MII) TXD[3:0] 40-37 32-29 (TXD[0] = TXDAT in GPSI mode) TX_ER ...
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... MDIO pin. 17 I/O MANAGEMENT directional port used to access management registers within the 78Q2132. This pin requires an external pull-up resistor as specified in IEEE-802.3. I PHY ADDRESS: Allows 31 configurable PHY addresses. The 78Q2132 always responds to data transactions via the MII interface when the PHYAD bits are all zero independent of the logic levels of the PHYAD pins ...
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... HomePNA/Ethernet Transceiver CONTROL AND STATUS (continued) NAME 80-PIN 64-PIN TECH[2:0] 63-65 51-53 MII_EN 74 MDI (Media Dependent Interface) NAME 80-PIN 802OP, 802ON 3, 5 802IP, 802IN 62, 61 NAME 80-PIN HLIP, HLIN 68, 67 HLOP, HLON 78, 80 TYPE DESCRIPTION I TECHNOLOGY technology ability of the chip which is reflected in MR0.13,8, MR1 ...
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... CRYSTAL INPUT: Should be connected MHz crystal. Otherwise, it doubles as the clock input pin and connects MHz clock source CRYSTAL OUTPUT PIN: Should be connected MHz crystal. When the clock comes from an external clock module not used. 9 78Q2132 1/10BASE-TX ...
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... HomePNA/Ethernet Transceiver MISCELLANEOUS PINS NAME 80-PIN GPIO0 19 GPIO1 20 INTR 43 POWER SUPPLY NAME 80-PIN V 8,13, CC 27,36, 45,51, 60, 79 GND 4,11, 12,28, 35,44, 46,52, 59,77 REFERENCE PIN RIBB 70 RIBB_RET 69 VBG 71 64-PIN TYPE DESCRIPTION N/A I/O GENERAL PURPOSE I/O PIN: This is an I/O pin that is configurable as an input or an output via management interface. ...
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... P1R4,5 HomePNA TX_PCOM P1R6,7 HomePNA RX_PCOM TYPE DESCRIPTION W Write-able by management SC Self clearing, write-able (0/1) Default value dependent on pin setting. The value in brackets indicates typical case. 11 78Q2132 1/10BASE-TX RESET VALUE (HEX) (0000) (1801) 000E 7121 (0061) 0000 0000 0000 0000 (0141) 0000 (0000) ...
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... The power-down state can also be achieved by setting PWRDN pin high. GLOBAL: Works for both HPNAEN=0,1 ISOLATE: When set, the 78Q2132 will present a high impedance on its MII output pins. This allows for multiple PHYs to be attached to the same MII interface. When the 78Q2132 is isolated, it stills responds to management transactions ...
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... TECH pins. HPNAEN=1: not applicable HPNAEN=0 COLLISION TEST: When this bit is set to one, the 78Q2132 will assert the COL signal in response to the assertion of TX_EN signal. Collision test is enabled regardless of the duplex mode of operation. HPNAEN=1: not applicable ...
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... HPNAEN=1: not applicable GLOBAL: Works for both HPNAEN=0,1 EXTENDED CAPABILITY: This bit is permanently set to logic one to indicate that the 78Q2132 provides an extended register set (MR2 and beyond). R, 000Eh ORGANIZATIONALLY UNIQUE IDENTIFIER: This value is 00- C0-39 for TDK Semiconductor Corporation. This translates to a value of 000Eh for this register ...
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... R, 00000 SELECTOR FIELD: This field contains the type of message sent by the link partner. For IEEE-802.3 compliant link partner transceiver, this field should be 00001. 15 1/10BASE-TX When internally set to logic one, the MII These bits are permanently The bit definition is the same as 78Q2132 ...
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... HomePNA/Ethernet Transceiver REGISTER DESCRIPTION MR6 - AUTO-NEGOTIATION EXPANSION REGISTER BIT SYMBOL 6.15:5 RSVD 6.4 PDF 6.3 LPNPA 6.2 NPA 6.1 PRX 6.0 LPANEGA MR16 - VENDOR SPECIFIC REGISTER BIT SYMBOL 16.15 RSVD 16.14 INT LEVEL 16.13 RSVD 16.12 RSVD 16.11 SQE TEST INHIBIT 16.10 NATURAL LOOPBACK 16.9 GPIO1_DAT 16.8 GPIO1_DIR 16.7 GPIO0_DAT (continued) TYPE DESCRIPTION R, 0 RESERVED: This bit is permanently tied low ...
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... REVERSE POLARITY: The reverse polarity is detected through 8 inverted 10BASE-T link. When the reverse polarity is detected, the 78Q2132 will invert the receive data path and set this bit to logic one if the feature is not disabled. If APOL is a logic 1, then this bit is write-able. Setting this bit forces the polarity to be reversed. ...
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... HomePNA/Ethernet Transceiver REGISTER DESCRIPTION MR17 - INTERRUPT CONTROL/STATUS REGISTER (continued) BIT SYMBOL TYPE 17.6 RXER INT RC, 0 17.5 PRX INT RC, 0 17.4 PDF INT RC, 0 17.3 LP-ACK INT RC, 0 17.2 LS-CHG INT RC, 0 17.1 RFAULT INT RC, 0 17.0 ANEG-COMP INT RC, 0 MR18 - DIAGNOSTIC REGISTER 18.15:13 RSVD R, 0 18.12 ANEGF R,0,RC 18 ...
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... PAGE SELECT: Selects the page of MII registers to be addressed and thus read and/or written. The default, 0, selects the normal MII registers. When 1, the HomePNA and internal registers are accessible. Registers 16, 17, 18, 19 are available (mapped) in both pages. 19 78Q2132 1/10BASE-TX The Master enable for HomePNA ...
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... HomePNA/Ethernet Transceiver REGISTER DESCRIPTION P1R0-14 - Programmable Register Map, PAGE 1 REGISTER SYMBOL 0 CONTROL 1 STATUS 2 IMASK (IMR) (continued) TYPE DESCRIPTION R/W The CONTROL register provides a common location for controlling the general operation of the PHY. This register is composed of the following bit fields: bit 0 = (reserved) ...
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... A non-null received PCOM will set the RxPCOM Valid bit of the ISTAT. Accessing the high word of the register clears this bit and allows over-writing of the register by subsequent received packets. 21 78Q2132 1/10BASE-TX Default 0x0000 ALL 0’s ALL 0’s ...
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... HomePNA/Ethernet Transceiver ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation above maximum rating may permanently damage the device. PARAMETER DC Supply Voltage Storage Temperature Pin Voltage Pin Current RECOMMENDED OPERATING CONDITIONS Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges: ...
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... 4. 4.0mA OH V 4. 4.0mA OL T 4. 4.0mA 3. 2.0mA OH V 3. 2.0mA OL T 3. 2.0mA 78Q2132 1/10BASE-TX MIN NOM MAX 0.8 2.0 -10 + -0 -0.4 CC 0.4 5 UNIT ...
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... MII Receive Interface CHARACTERISTICS Receive Output Delay: RX_CLK to RXD[3:0], RX_DV, RX_ER RX_CLK Duty-Cycle (continued) FIGURE 1: Transmit Inputs to the 78Q2132 SYMBOL CONDITIONS CKIN FIGURE 2: Receive Outputs from the 78Q2132 SYMBOL CONDITIONS RX DLY 24 MIN NOM MAX UNIT MIN ...
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... MDIO Interface Input Timing CHARACTERISTICS Setup Time: MDC to MDIO Hold Time: MDC to MDIO Max Frequency: MDC FIGURE 4: MDIO as an Output from the 78Q2132 MDIO Interface Output Timing CHARACTERISTICS MDC to MDIO data delay MDIO output from high Z to driven after MDC MDIO output from driven to ...
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... HomePNA/Ethernet Transceiver FIGURE 5: MDIO Interface Output Timing 26 ...
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... The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. PARAMETER Peak Differential Output Signal Link Pulse Width Start-of-Idle Pulse Width HomePNA/Ethernet Transceiver (continued) CONDITION CONDITION All data patterns 27 78Q2132 1/10BASE-TX MIN NOM MAX UNIT ...
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... HomePNA/Ethernet Transceiver ELECTRICAL SPECIFICATIONS 10BASE-T Transmitter The specifications in the following table are not tested during production test. They are included for information only. PARAMETER Output return loss Harmonic Content Output Impedance Balance Peak Common-mode Output Voltage Common-mode rejection Common-mode rejection jitter ...
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... The maximum values of the waveform after 1 usec from when it first crosses the 5 mV threshold does not exceed the mask of Figure 6 – HomePNA Transmit mask for times greater than 1usec. Figure 7 – HomePNA Transmit mask for times greater than 1usec HomePNA/Ethernet Transceiver HPNA TX Mask 7.5 Mhz Figure 6 – HomePNA Transmit Pulse Shape 29 78Q2132 1/10BASE-TX ...
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... HomePNA/Ethernet Transceiver ELECTRICAL SPECIFICATIONS The output power spectrum meets the spectral mask of Figure 8 – HomePNA PSD Mask with a termination of 100 ohms and back-to-back Ethernet packets of 1518 bytes length with random data. The resolution bandwidth shall be 100 kHz. The specified PSD levels include thermal noise. The power level requirements below 1.1 MHz allow 1M8 PHY stations to interoperate with G ...
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... Gaussian Noise level (mV peak ± VALUE 25.00000 Parallel Resonance, Fundamental Mode > below main within 500 kHz 31 78Q2132 1/10BASE-TX MIN NOM MAX UNIT 20m 1.2 500 100 Packet Error Rate (PER) 0 0.1 % Packet Error Rate (PER) 0.01% 0.5% UNITS ...
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... HomePNA/Ethernet Transceiver ELECTRICAL SPECIFICATIONS 10BASE-T ISOLATION TRANSFORMERS Two simple isolation transformers are all that are required at the line interface, but transformers with integrated common-mode choke are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics: ...
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... MECHANICAL DRAWINGS HomePNA/Ethernet Transceiver 33 78Q2132 1/10BASE-TX ...
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... HomePNA/Ethernet Transceiver MECHANICAL DRAWINGS (continued) 34 ...
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... PACKAGE PIN DESIGNATIONS (Top View) HomePNA/Ethernet Transceiver CAUTION: Use handling procedures necessary 64-Lead Thin Quad Flatpack 78Q2132 35 78Q2132 1/10BASE-TX for a static sensitive component ...
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... TDK Semiconductor Corporation, 2642 Michelle Drive, Tustin, CA 92780-7019, (714) 508-8800, FAX: (714) 508-8877 TDK Semiconductor Corporation (continued) 80-Lead TQFP 78Q2132 36 CAUTION: Use handling procedures necessary for a static sensitive component 08/08/00 – Rev. A ...