AT91SAM7XC512 ATMEL Corporation, AT91SAM7XC512 Datasheet
AT91SAM7XC512
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AT91SAM7XC512 Summary of contents
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... In-circuit Emulation, Debug Communication Channel Support • Internal High-speed Flash – 512 Kbytes (AT91SAM7XC512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (AT91SAM7XC256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (AT91SAM7XC128) Organized in 512 Pages of 256 Bytes (Single Plane) – ...
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... Seventeen Peripheral DMA Controller (PDC) Channels • One Advanced Encryption System (AES) – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications (AT91SAM7XC512) – 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications (AT91SAM7XC256/128) – Buffer Encryption/Decryption Capabilities with PDC • ...
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... AT91SAM7XC/512/256/128 Preliminary Summary 1. Description Atmel's AT91SAM7XC512/256/128 is a member of a series of highly integrated Flash microcon- trollers based on the 32-bit ARM RISC processor. It features 512/256/128 Kbyte high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, a CAN controller, an AES 128 Encryption accelerator and a Triple Data Encryption System. A complete set of system functions minimizes the number of external components ...
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... AT91SAM7XC512/256/128 Block Diagram Figure 2-1. JTAGSEL IRQ0-IRQ1 PCK0-PCK3 VDDCORE VDDFLASH VDDCORE SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADVREF AT91SAM7XC/512/256/128 Preliminary Summary 4 AT91SAM7XC512/256/128 Block Diagram TDI TDO ICE JTAG TMS SCAN TCK System Controller TST ...
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AT91SAM7XC/512/256/128 Preliminary Summary 3. Signal Description Table 3-1. Signal Description List Signal Name Function Voltage Regulator and ADC Power VDDIN Supply Input VDDOUT Voltage Regulator Output VDDFLASH Flash and USB Power Supply VDDIO I/O Lines Power Supply VDDCORE Core Power ...
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Table 3-1. Signal Description List (Continued) Signal Name Function DDM USB Device Port Data - DDP USB Device Port Data + SCK0 - SCK1 Serial Clock TXD0 - TXD1 Transmit Data RXD0 - RXD1 Receive Data RTS0 - RTS1 Request ...
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AT91SAM7XC/512/256/128 Preliminary Summary Table 3-1. Signal Description List (Continued) Signal Name Function AD0-AD3 Analog Inputs AD4-AD7 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference PGMEN0-PGMEN1 Programming Enabling PGMM0-PGMM3 Programming Mode PGMD0-PGMD15 Programming Data PGMRDY Programming Ready PGMNVALID Data Direction PGMNOE ...
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... Package The AT91SAM7XC512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHS-compliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 tion is given in the Mechanical Characteristics section of the full datasheet. Figure 4-1. AT91SAM7XC/512/256/128 Preliminary Summary 8 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip- 100-lead LQFP Package Outline (Top View) ...
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AT91SAM7XC/512/256/128 Preliminary Summary 4.2 100-lead LQFP Pinout Table 4-1. Pinout in 100-lead LQFP Package 1 ADVREF 26 2 GND 27 3 AD4 28 4 AD5 29 5 AD6 30 6 AD7 31 7 VDDOUT 32 8 VDDIN 33 9 PB27/AD0 ...
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TFBGA Package Outline Figure 4-2 description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-2. 4.4 100-ball TFBGA Pinout Table 4-2. Pinout in 100-ball TFBGA Package Pin Signal Name Pin A1 PA22/PGMD10 C6 A2 ...
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... Power Consumption The AT91SAM7XC512/256/128 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current. ...
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... For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 5.4 Typical Powering Schematics The AT91SAM7XC512/256/128 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. 1 shows the power schematics to be used for USB bus-powered systems. ...
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... AT91SAM7XC512/256/128 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. ...
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I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive permanently. The remaining I/O lines can draw only 8 mA. However, the total current ...
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AT91SAM7XC/512/256/128 Preliminary Summary 7. Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM – Thumb • Three-stage pipeline ...
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Embedded Flash Controller – Embedded Flash interface three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and ...
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... AT91SAM7XC/512/256/128 Preliminary Summary 8. Memory 8.1 AT91SAM7XC512 • 512 Kbytes of dual-plane Flash Memory – 2 contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase – ...
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... Figure 8-1. AT91SAM7XC512/256/128 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256 MBytes 0x0FFF FFFF 0x1000 0000 Undefined 14 x 256 MBytes (Abort) 3,584 MBytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 256 MBytes 0xFFFF FFFF AT91SAM7XC/512/256/128 Preliminary Summary 18 Internal Memory Mapping 0x0000 0000 ...
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... After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.4.2 Internal ROM The AT91SAM7XC512/256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA program. 8.4.3 Internal Flash • ...
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... Embedded Flash 8.5.1 Flash Overview • The Flash of the AT91SAM7XC512 is organized in two banks (dual plane) 0f 1254 pages of 256 bytes. The 524, 288 bytes are organized in 32-bit words. • The Flash of the AT91SAM7XC256 is organized in 1024 pages of 256 bytes (single plane). It reads as 65,536 32-bit words. ...
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... Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.5.4 Security Bit Feature The AT91SAM7XC512/256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast 6209BS–ATARM–03-Sep-06 ...
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Flash Programming Interface, is forbidden. This ensures the confidentiality of the code pro- grammed in the Flash. This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can ...
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AT91SAM7XC/512/256/128 Preliminary Summary • Communication via the USB Device Port is limited to an 18.432 MHz crystal. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped at address ...
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System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and ...
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AT91SAM7XC/512/256/128 Preliminary Summary Figure 9-1.System Controller Block Diagram NRST XIN XOUT PLLRC PA0-PA30 PB0-PB30 6209BS–ATARM–03-Sep-06 System Controller irq0-irq1 Advanced fiq Interrupt Controller periph_irq[2..19] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK Debug periph_nreset Unit dbgu_rxd Periodic MCK debug Interval periph_nreset ...
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... Brownout Detector and Power-on Reset The AT91SAM7XC512/256/128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power- down sequences or if brownouts occur on the power supplies. ...
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AT91SAM7XC/512/256/128 Preliminary Summary 9.2 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between ...
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Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • four programmable ...
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... Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of – Chip ID is 0x271C 0A40 (VERSION 0) for AT91SAM7XC512 – Chip ID is 0x271B 0940 (VERSION 0) for AT91SAM7XC256 – Chip ID is 0x271A 0740 (VERSION 0) for AT91SAM7XC128 9 ...
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Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controllers • Two PIO Controllers, each controlling 31 I/O lines • Fully programmable through set/clear registers • Multiplexing of two peripheral functions per I/O line • For each I/O line ...
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... FFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in 10.2 Peripheral Identifiers The AT91SAM7XC512/256/128 embeds a wide range of peripherals. Peripheral Identifiers of the AT91SAM7XC512/256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID 0 ...
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... Peripheral Multiplexing on PIO Lines The AT91SAM7XC512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral func- tions Some of them can also be multiplexed with the analog inputs of the ADC Controller ...
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AT91SAM7XC/512/256/128 Preliminary Summary 10.4 PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A PA0 RXD0 PA1 TXD0 PA2 SCK0 PA3 RTS0 PA4 CTS0 PA5 RXD1 PA6 TXD1 PA7 SCK1 PA8 RTS1 ...
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PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A PB0 ETXCK/EREFCK PB1 ETXEN PB2 ETX0 PB3 ETX1 PB4 ECRS PB5 ERX0 PB6 ERX1 PB7 ERXER PB8 EMDC PB9 EMDIO PB10 ...
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AT91SAM7XC/512/256/128 Preliminary Summary 10.6 Ethernet MAC • DMA Master on Receive and Transmit Channels • Compatible with IEEE Standard 802.3 • 10 and 100 Mbit/s operation • Full- and half-duplex operation • Statistics Counter Registers • MII/RMII interface to the ...
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One, two or three bytes for slave address • Sequential read/write operations 10.9 USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode ...
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AT91SAM7XC/512/256/128 Preliminary Summary – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs • Five internal clock inputs, as defined in Table 10-4. TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 ...
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... Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) • 128-bit (AT91SAM7XC256/128) or 128-bit/192-bit/256-bit (AT91SAM7XC512) Cryptographic Key • 12-clock Cycles Encryption/Decryption Processing Time (AT91SAM7XC256/128) • 12/13/14-clock Cycles Encryption/Decryption Processing Time (AT91SAM7XC512) • Support of the Five Standard Modes of Operation specified in the NIST Special Publication 800-38A: – Electronic Codebook (ECB) – ...
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AT91SAM7XC/512/256/128 Preliminary Summary • 64-bit Cryptographic Key • Two-key or Three-key Algorithms • 18-clock Cycles Encryption/Decryption Processing Time for DES • 50-clock Cycles Encryption/Decryption Processing Time for TDES • Support the Four Standard Modes of Operation specified in the FIPS ...
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Package Drawings Figure 11-1. LQFP Package Drawing AT91SAM7XC/512/256/128 Preliminary Summary 40 6209BS–ATARM–03-Sep-06 ...
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AT91SAM7XC/512/256/128 Preliminary Summary Table 11-1. Symbol θ1 θ2 θ aaa bbb ccc ddd 6209BS–ATARM–03-Sep-06 100-lead LQFP Package Dimensions Millimeter Min Nom Max ...
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Figure 11-2. 100-TFBGA Package Drawing All dimensions are in mm AT91SAM7XC/512/256/128 Preliminary Summary 42 6209BS–ATARM–03-Sep-06 ...
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... AT91SAM7XC/512/256/128 Preliminary Summary 12. AT91SAM7XC512/256/128 Ordering Information Table 12-1. Ordering Information Ordering Code AT91SAM7XC512-AU AT91SAM7XC512-CU AT91SAM7XC256-AU AT91SAM7XC256-CU AT91SAM7XC128-AU AT91SAM7XC128-CU 13. Export Regulations Statement These commodities, technology or software will be exported from France and the applicable Export Administration Regulations will apply. French, United States and other relevant laws, reg- ulations and requirements regarding the export of products may restrict sale, export and re- export of these products ...
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... Revision History Table 13-1. Revision History Doc. Rev Comments First issue - Unqualified on Intranet 6209S Legal page updated.Qualified on Intranet Added AT91SAM7XC512 to product Reformatted Memories Reordered sub sections in Peripherals Consolidated Memory Mapping in Added package drawings 6209BS Consolidated Memory Mapping in Added TFBGA information 4.4 on page 10 and “ ...
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... Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2006 Atmel Corporation. All rights reserved. Atmel ™ istered trademarks SAM-BA and others are trademarks of Atmel Corporation or its subsidiaries. ARM are registered trademarks or trademarks of ARM Limited. Other terms and product names may be the trademarks of others. Atmel Operations Memory ...