PN511 NXP Semiconductors, PN511 Datasheet
PN511
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PN511 Summary of contents
Page 1
... FeliCa framing and error detection like CRC. The PN511 supports contactless communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions. In Card Operation mode, the PN511 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO 14443A/Mifare card interface scheme. ...
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... NXP Semiconductors Additionally, the PN511 transceiver IC offers the possibility to communicate directly to an NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092 NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error detection ...
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... Programmable timer „ Internal oscillator to connect 27.12 MHz quartz „ 2.5-3.6 V power supply „ CRC Co-processor „ Free programmable I/O pins „ Internal self test 082733 Product short data sheet Rev. 3.3 — 13 June 2007 PN511 Transmission Module © NXP B.V. 2007. All rights reserved ...
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... LOW RESET [ level detector bit RCVOff = bit RCVOff = 1 DD [5] [4][6][8] Continuous Wave . DD Rev. 3.3 — 13 June 2007 PN511 Transmission Module Min Typ Max Unit 2.5 - 3.6 V 1 ...
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... The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. The Data mode detector detects a Mifare, FeliCa or NFCIP-1 mode in order to prepare the internal receiver to demodulate signals, which are sent to the PN511. The communication (S transfer speeds above 424 kbit/s and digital signals to communicate to a secure smart card IC ...
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... Random Number Generator Amplitude Rating Reference Voltage Analog Test MUX and DAC VMID AUX1,2 Fig 1. PN511 Block diagram 082733 Product short data sheet ALE PVDD 8 bit Parallel, SPI, UART, I2C Interface Control (incl. Automatic Interface Detection & Synchronisation) State Machine ...
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... Transparent top view terminal 1 index area PVDD 5 PN511 DVDD 6 7 DVSS PVSS 8 9 NRSTPD SIGIN 10 Transparent top view Rev. 3.3 — 13 June 2007 PN511 Transmission Module 24 ALE 23 IRQ 22 OSCOUT 21 OSCIN 20 AUX2 19 AUX1 18 AVSS 17 RX SOT617-1 30 NCS 29 ALE 28 NRD 27 ...
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... Remark: For serial interfaces this pins can be used for test signals or I/Os Address Line 082733 Product short data sheet osc digital host controller interface, these pins 2 C address. Rev. 3.3 — 13 June 2007 PN511 Transmission Module = 27.12 MHz). © NXP B.V. 2007. All rights reserved ...
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... Crystal Oscillator Output: Output of the inverting amplifier of the oscillator. IRQ 26 O Interrupt Request: output to signal an interrupt event NWR 27 I Not Write: strobe to write data (applied D7) into the PN511 register NRD 28 I Not Read: strobe to read data from the PN511 register (applied D7) ALE 29 I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch when HIGH ...
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... Note: All indicated modulation indices and modes in this chapter are system parameters. This means that beside the IC settings a suitable antenna tuning is required to achieve the optimum performance. 8.1 Reader/Writer mode Generally 2 Reader/Writer modes are supported. The PN511 can act as a reader/writer for ISO 14443A/Mifare or FeliCa cards. Battery Reader / Writer Fig 4 ...
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... PICC o PN511 (receive data from a card) The contactless UART of PN511 and a dedicated external host controller are required to handle the complete Mifare/ISO 14443A/Mifare protocol. 8.1.1.1 Data Coding and framing according to ISO 14443A/Mifare The internal CRC co-processor calculates the CRC value according to the definitions given in the ISO 14443A part 3 and handles parity generation internally according to the transfer speed ...
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... The CRC calculation is done according to the FeliCa definitions with the MSB first. To transmit data on the RF interface, the host controller has to send the Len- and data- bytes to the PN511's FIFO buffer. The preamble and the sync bytes are generated by the PN511 automatically and must not be written to the FIFO by the host controller. The PN511 performs internally the CRC calculation and adds the result to the data frame ...
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... Communication mode or using a self generated and self modulated RF field for Active Communication mode. In order to fully support the NFCIP-1 standard the PN511 supports the Active and Passive Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the NFCIP-1 standard. ...
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... Initiator o Target According to Target o Initiator The contactless UART of PN511 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN511 supports these transfer speeds only with dedicated external circuits. ...
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... Initiator o Target According to Target o Initiator According to The contactless UART of PN511 and a dedicated host controller are required to handle the NFCIP-1 protocol. Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The PN511 supports these transfer speeds only with dedicated external circuits. ...
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... PN511 can generate an answer in a load modulation scheme according to the ISO 14443A/Mifare or FeliCa interface description. Note: The PN511 does not support a complete card protocol. This has to be handled by a dedicated card SAM or a host controller. The card-SAM is optional. Reader/ Writer for FeliCa Generates RF Fig 11 ...
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... MHz/16 frequency bit coding Manchester coding Transfer speed Modulation on reader side bit coding Bitlength Load modulation on PN511 side bit coding Rev. 3.3 — 13 June 2007 PN511 Transmission Module Mifare Higher transfer speeds 212 kbit/s 424 kbit/s 100% ASK 100% ASK ...
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... NXP Semiconductors 9. Application design-in information The figure below shows a typical circuit diagram, using a complementary antenna connection to the PN511. The antenna tuning and RF part matching is described in the application note PN511 transceiver IC; Antenna and RF Design Guide DVDD PVDD PVSS NRSTPD Host Interface Controller ...
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... J ESDH ESD Susceptibility (Human Body model) ESDM ESD Susceptibility (Machine model) ESDC ESD Susceptibility (Charge Device model) 11. Package information The PN511 can be delivered in 2 different packages. Table 14. Package Information Package Remarks HVQFN32 8-bit parallel interface not supported HVQFN40 Supports the 8-bit parallel interface 12 ...
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... Product short data sheet Preliminary short data sheet Objective short data sheet Rev. 3.3 — 13 June 2007 PN511 Transmission Module Supersedes Revision 3.2 Revision 3.1 updated from PN5110A0HN1/C1 to Revision 3.0 Type of Pin 15: 0 -> PWR 12: renamed Table Title Revision 2.0 Revision 1.0 - © NXP B.V. 2007. All rights reserved. ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Mifare — trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 3.3 — 13 June 2007 PN511 Transmission Module © NXP B.V. 2007. All rights reserved ...
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... Communication overview for FeliCa reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 7. FeliCa framing and coding . . . . . . . . . . . . . . . .12 Table 8. Start Value for the CRC Polynomial: (00h), (00h .12 17. Figures Fig 1. PN511 Block diagram . . . . . . . . . . . . . . . . . . . . . .6 Fig 2. Pinning configuration HVQFN32 (SOT617- Fig 3. Pinning configuration HVQFN40 (SOT618 Fig 4. Reader/Writer mode .10 Fig 5. ISO 14443A/Mifare Reader/Writer mode communication diagram ...