HMP8154 Intersil Corporation, HMP8154 Datasheet
HMP8154
Related parts for HMP8154
HMP8154 Summary of contents
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... Data Sheet NTSC/PAL Encoders The HMP8154 and HMP8156A NTSC and PAL encoders are designed for use in systems requiring the generation of high-quality NTSC and PAL video from digital image data. YCbCr or RGB digital video data drive the P0-P23 inputs. Overlay inputs are processed and the data is 2x upsampled. ...
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... SAMPLE CONVERSION SA SCL HOST INTERFACE SDA RESET HSYNC VSYNC VIDEO BLANK TIMING CONTROL CLK CLK2 FIELD OVERLAY PROCESSING FLICKER 2X FILTER UPSCALING (HMP8154 (SIF MODE) ONLY) CAPTIONING PROCESSING (OPTIONAL) LP FILTER UPSAMPLE 4:4:4 TO 8:8:8 LP FILTER Cb/Cr CHROMA MODULATION CLOSED INTERNAL 1.225V REFERENCE DAC DAC ...
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... When enabled, the encoder passes the pixel data after overlay processing through a three line flicker filter. Pixel Data Input Formats The HMP8154 accepts pixel data via the P0-P23 input pins. The definition of each pixel input pin is determined by the input format selected in the input format register. The defi ...
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... M1 and M0 indicate the mixing level between the pixel inputs and the overlay inputs pixel-by-pixel basis. M1 and M0 are ignored if OL2-OL0 = 000. Otherwise, they select the percentage of each color to sum as shown in Table 3. 4 HMP8154, HMP8156A TABLE 1. PIXEL DATA INPUT FORMATS 8-BIT 4:2:2 YCBCR BT ...
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... YCbCr and BT.656 input formats and 2X upscaling of SIF input may not be used when the flicker filter is enabled. The HMP8154 uses internal line stores and a 3 tap FIR filter to reduce flickering. The filter coefficients are 0.25, 0.5, and 0.25. At the start and end of each field, the coefficients are modifi ...
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... CLK2. As outputs, BLANK, HSYNC, and VSYNC are output following the rising edge of CLK2. If the CLK pin is configured as an input ignored. If configured as an output one-half the CLK2 frequency. 6 HMP8154, HMP8156A VIDEO TIMING CONTROL (NOTE 2) OVERLAY DATA INPUT SAMPLE Same edge that ...
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... As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. In these modes of operation, CLK is one-half the CLK2 frequency. 7 HMP8154, HMP8156A PIXEL 0 ...
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... FIGURE 4. PIXEL AND OVERLAY INPUT TIMING - NORMAL 16-BIT RGB CLK2 CLK RGB 0 P0-P24 BLANK (INPUT) BLANK (OUTPUT) FIGURE 5. PIXEL AND OVERLAY INPUT TIMING - NORMAL 24-BIT RGB 8 HMP8154, HMP8156A PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 ...
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... BLANK (OUTPUT) FIGURE 8. PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITH 2X UPSAMPLING 9 HMP8154, HMP8156A As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. CLK is one-fourth the CLK2 frequency ...
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... BLANK (OUTPUT) FIGURE 11. PIXEL AND OVERLAY INPUT TIMING - 24-BIT RGB WITH FLICKER FILTERING 10 HMP8154, HMP8156A As inputs, BLANK, HSYNC, and VSYNC are latched on each rising edge of CLK2. As outputs, BLANK, HSYNC, and VSYNC are output following the rising edge of CLK2. If the CLK pin is configured as an input ignored. If configured as an output one-half the CLK2 frequency ...
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... VSYNC, and BLANK signals must be configured as outputs. Video Timing Control Regardless of the input mode, the output video timing of the HMP8154/HMP8156A 59.94 fields per second (interlaced). For normal and 2X upscaling modes, the pixel input timing 59.94 fields per second; with the fl ...
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... CLK2 cycles. The delay from BLANK to the start or end of active video is an additional one-half CLK cycle when the blank timing select bit is cleared. The active video may also appear to end early or start late since the HMP8154/HMP8156A controls the blanking edge rates. START H BLANK ...
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... The Y 6.0MHz lowpass filter response is shown in Figure 18. At this point, the HMP8154/HMP8156A also scales the Y data to generate the proper output levels for the various video standards The HMP8154/HMP8156A lowpass filters the Cb and Cr data to 1 ...
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... NTSC SQUARE PIXEL CLK2 = 24.54MHz -40 -50 - FREQUENCY (MHz) FIGURE 18A. FULL SPECTRUM . 14 HMP8154, HMP8156A TABLE 7. TYPICAL VIDEO TIMING PARAMETERS HBLANK REGISTER VALUES ACTIVE START END 720 842 (0x34a) 122 (0x7a) 720 853 (0x355) 133 (0x85) 720 842 (0x34a) ...
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... If the registers are not updated, the encoder resends the previously loaded values. The HMP8154/HMP8156A provides a write status bit for each captioning line. The encoder clears the write status bit to ‘0’ when captioning is enabled and both bytes of the captioning data register have been written. The encoder sets the write status bit to ‘ ...
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... VREF must be chosen such that it is within the part’s operating range; RSET must be chosen such that the maximum output current is not exceeded. If the VREF pin is not connected, the HMP8154/HMP8156A provides an internal reference voltage. Otherwise, the applied voltage overdrives the internal reference external reference is used, it must decoupled from any power supply noise ...
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... I written or read by the host processor at any time. However, some of the bits and words are read only or reserved and data written to these bits is ignored. Table 10 lists the HMP8154/HMP8156A’s internal registers. Their bit descriptions are listed in Tables 11-30 interface ...
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... Input Resolution This bit must be set to “0” during BT.656 input mode and when the flicker filter is enabled Full resolution (2X upscaling disabled SIF resolution (2X upscaling enabled) 18 HMP8154, HMP8156A TABLE 11. PRODUCT ID REGISTER SUB ADDRESS = 00 H DESCRIPTION TABLE 12. OUTPUT FORMAT REGISTER SUB ADDRESS = 01 ...
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... Active low (low during vertical sync) Polarity 1 = Active high (high during vertical sync) 0 FIELD 0 = Active low (low during odd fields) Polarity 1 = Active high (high during odd fields) 19 HMP8154, HMP8156A TABLE 14. VIDEO PROCESSING REGISTER SUB ADDRESS = 03 H DESCRIPTION TABLE 15. TIMING I/O REGISTER #1 SUB ADDRESS = 04 H DESCRIPTION ...
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... Enabled Output Mode 1 = Disabled 1 Y Enabled Output Mode 1 = Disabled 0 C Enabled Output Mode 1 = Disabled 20 HMP8154, HMP8156A TABLE 16. TIMING I/O REGISTER #2 SUB ADDRESS = 05 H DESCRIPTION TABLE 17. AUXILIARY DATA ENABLE REGISTER SUB ADDRESS = 06 H DESCRIPTION TABLE 18. HOST CONTROL REGISTER SUB ADDRESS = 0F H DESCRIPTION RESET ...
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... It specifies the horizontal count (in 1x clock cycles) at which to (Horizontal) start ignoring pixel data each scan line. The leading edge of HSYNC is count 020 ister is ignored unless BLANK is configured as an output. 21 HMP8154, HMP8156A TABLE 19. CLOSED CAPTION_21A DATA REGISTER SUB ADDRESS = 10 H DESCRIPTION TABLE 20 ...
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... The leading edge of VSYNC at the start of an odd field is count 000 follow standard NTSC or PAL line numbering). This register is ignored unless BLANK is con- figured as an output. 22 HMP8154, HMP8156A TABLE 25. END H_BLANK REGISTER SUB ADDRESS = 22 H DESCRIPTION TABLE 26 ...
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... Field Detect This bit is cascaded with Field Detect Window Size Low to form a 9-bit Field Detect Window Size Window Size High value. This bit is ignored unless HSYNC and VSYNC are configured as inputs. 23 HMP8154, HMP8156A TABLE 29. FIELD CONTROL REGISTER 1 SUB ADDRESS = 26 H DESCRIPTION TABLE 30 ...
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... Pin Descriptions PIN PIN INPUT/ NAME NUMBER OUTPUT 58, 55-43, P0-P15 38, 37 32-27, 23, P16-P23 22 RESV 21 FIELD 34 HSYNC 35 VSYNC 36 BLANK 33 24 HMP8154, HMP8156A HMP8154/HMP8156A (PQFP) TOP VIEW VAA 1 VAA 2 Y/G 3 GND 4 VAA 5 GND 6 C/B 7 GND 8 VAA 9 GND ...
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... COMP 2 63 VAA GND 25 HMP8154, HMP8156A I/O 1X pixel clock input/output input, this clock must be free-running and synchronous to the clock signal on the CLK2 pin output, this pin may drive a maximum of one LS TTL load. CLK is generated by dividing CLK2 by two or four, depending on the mode. If not driven, the circuit for this pin should include a 4-12k VAA ...
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... Output Logic Low Voltage PARAMETERS, ANALOG OUTPUTS DAC Resolution Integral Nonlinearity, INL Differential Nonlinearity, DNL Output Current Output Impedance Output Capacitance 26 HMP8154, HMP8156A Thermal Information Thermal Resistance (Typical, Note 3) PQFP Package Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 Maximum Storage Temperature Range . . . . . . . . . . - Vapor Phase Soldering, 1 Minute ...
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... The supply voltage rejection is the relative variation of the full-scale output driving a 37.5 load for a 0.5% supply variation: PSRR = 20 x log ( OUT 27 HMP8154, HMP8156A = 25 A TEST CONDITION (Note 4) VREF unconnected, RSET = 133 VREF = 1.230V (Figure 37), RSET = 140 Pin not driven, using internal reference Pin connected to external reference shown in Figure 37 ...
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... Wfm ---> PEDESTAL -30.0 NOISE LEVEL = -79.9dB RMS -35.0 -40.0 -45.0 -50.0 -55.0 -60.0 -65.0 -70.0 -75.0 -80.0 -85.0 -90.0 -95.0 -100.0 1.0 2.0 3.0 AVERAGE (MHz) FIGURE 22. NOISE SPECTRUM (NTSC) 28 HMP8154, HMP8156A APL = 44.3% 4.0 5.0 SETUP 7.5% FIGURE 23. NTSC COLOR BAR VECTOR SCOPE FIGURE 24. NTSC FCC COLOR BAR SYSTEM LINE ANGLE (DEG) 0.0 GAIN x1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE ...
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... AVERAGE FIGURE 25. LUMINANCE NON LINEARITY (NTSC) LINE JITTER (LINE 20 TO 250) FIGURE 27. H SYNC JITTER IN A FRAME (NTSC) AVERAGE FIGURE 29. NOISE SPECTRUM (PAL) 29 HMP8154, HMP8156A (Continued) wfm ---> 5 STEP PEAK-TO-PEAK = 2.1 LINE FREQUENCY ERROR 100.0 99.8 -0.4 LINE FREQUENCY 15.734 (kHz) FIELD FREQUENCY 59.94 (Hz) ...
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... AVERAGE FIGURE 32. LUMINANCE NON LINEARITY (PAL) 30 HMP8154, HMP8156A (Continued) FIGURE 31. COLORBAR (PAL) wfm ---> 5 STEP PEAK-TO-PEAK = 1.4 LINE FREQUENCY ERROR 100.0 99.8 -0.4 LINE FREQUENCY 15.625 (kHz) FIELD FREQUENCY 50.00 (Hz) AVERAGE OFF 4TH 5TH Wfm ---> COLOR BAR 0.00 (%) -0.2 0.0 0.2 (%) FIGURE 33. LINE FREQUENCY (PAL) ...
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... A common ground plane for all devices, including the HMP8154/HMP8156A, is recommended. However, placing the encoder on an electrically connected GND peninsula reduces noise levels. All GND pins on the HMP8154/HMP8156A must be connected to the ground plane. Typical power and ground planes are shown in Figure 36. ...
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... AA External Reference Voltage If an external reference voltage is used, its circuitry should receive power from the same plane as the HMP8154/ HMP8156A. The external VREF must also be stable and well decoupled from the power plane. An example VREF circuit using a band gap reference diode is shown in Figure 37. ...
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... The board allows the encoder’s operation and performance to be observed and measured. The HMP8154EVAL1 board has a 50 pin, two row receptacle which allows connection into an existing system. The connector provides access to all of the encoder’s digital inputs and outputs ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 34 HMP8154, HMP8156A Q64.14x14 64 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE -D- SYM- BOL A A1 -B- ...