HMP351U6MMP8C Hynix Semiconductor, HMP351U6MMP8C Datasheet
HMP351U6MMP8C
Related parts for HMP351U6MMP8C
HMP351U6MMP8C Summary of contents
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... OCD (Off-Chip Driver Impedance Adjustment) • ODT (On-Die Termination) ORDERING INFORMATION Part Name HMP351U6MMP8C - Y5/S6 HMP351U7MMP8C - Y5/S6 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / May 2008 • ...
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SPEED GRADE & KEY PARAMETERS C4 (DDR2-533) Speed @CL3 400 Speed @CL4 533 Speed @CL5 - Speed @CL6 - CL-tRCD-tRP 4-4-4 ADDRESS TABLE Density Organization Ranks 4GB 512M 4GB 512M Rev. 0.1 / May ...
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Input/Output Functional Description Symbol Type Polarity Differential SSTL CK[2:0], CK[2:0] Crossing SSTL Active High CKE[1:0] SSTL Active Low S[1:0] RAS, CAS, SSTL Active Low WE SSTL Active High ODT[1:0] Vref Supply V Supply DDQ SSTL - BA[2:0] A[9:0], A10/AP, SSTL ...
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PIN CONFIGURATION 1 pin 121 pin PIN ASSIGNMENT Pin Name Pin Name 1 VREF 41 VSS 2 VSS 42 NC(CB0)* 3 DQ0 43 NC(CB1)* 4 DQ1 44 VSS 5 VSS 45 NC(DQS8)* 6 DQS0 46 NC(DQS8)* 7 DQS0 47 VSS ...
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PIN ASSIGNMENT(Continued) Pin Name Pin Name 23 VSS DQ16 64 VDD 25 DQ17 65 VSS 26 VSS 66 VSS 27 DQS2 67 VDD 28 DQS2 VSS 69 VDD 30 DQ18 70 A10/AP 31 DQ19 ...
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FUNCTIONAL BLOCK DIAGRAM 4GB(512Mbx64) - HMP351U6MFP8C /S0 / DQS0 DQS0 DM0 DM /CS DQS /DQS / DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 I/ O ...
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FUNCTIONAL BLOCK DIAGRAM 4GB(512Mbx72) - HMP351U72MFP8C /S0 / DQS0 DQS0 DM0 ...
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ABSOLUTE MAXIMUM RATINGS Parameter Voltage on V pin relative to Vss DD Voltage on V pin relative to Vss DDQ Voltage on any pin relative to Vss Operation Conditions and Environmental Parameters Parameter DIMM Operating temperature(ambient) Storage Temperature Storage Humidity(without ...
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INPUT DC LOGIC LEVEL Parameter Symbol dc Input logic HIGH V (DC Input logic LOW V (DC) IL INPUT AC LOGIC LEVEL Parameter Symbol AC Input logic High V (AC Input logic Low V (AC) IL ...
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Differential Input AC logic Level Symbol Parameter V (ac) ac differential input voltage ID V (ac) ac differential cross point voltage (DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, ...
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OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS Symbol V Output Timing Measurement Reference Level OTR Note : 1. The VDDQ of the device under test is referenced. OUTPUT DC CURRENT DRIVE Symbol I Output Minimum Source DC Current OH(dc) I ...
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PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°C) 4GB : HMP351U6MFP8C Pin CK, CK CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS 4GB : HMP351U7MFP8C Pin CK, CK CKE, ODT, CS Address, RAS, CAS, WE DQ, DM, DQS, DQS Notes : ...
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U - DIMM : HMP351U6MFP8C Y5 Symbol (DDR2 667@CL 5) 1040 IDD0 1200 IDD1 128 IDD2P 720 IDD2Q 800 IDD2N 560 IDD3P(F) 288 IDD3P(S) 880 IDD3N 1760 IDD4R 1600 IDD4W 2240 IDD5B 128 IDD6 2760 IDD7 ...
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IDD MEASUREMENT CONDITIONS Symbol Operating one bank active-precharge current CK(IDD RC(IDD), t RAS = t RAS- IDD0 min(IDD);CKE is HIGH HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs ...
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Electrical Characteristics & AC Timings Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin Speed DDR2-800(S5) Bin(CL-tRCD-tRP) 5-5-5 Parameter min CAS Latency 5 tRCD 12.5 tRP 12.5 tRC 57.5 tRAS 45 AC Timing Parameters by Speed Grade Parameter Data-Out edge ...
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Parameter Address and control input setup time Address and control input hold time Read preamble Read postamble Auto-Refresh to Active/Auto-Refresh command period Row Active to Row Active Delay for 1KB page size Row Active to Row Active Delay for 2KB ...
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Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input setup time (differential strobe) DQ and DM input hold time ...
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Parameter CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time tDAL Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to ...
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PACKAGE OUTLINE 512Mx 64 - HMP351U6MFP8C 4.0±0.1 5.175 63.0 Detail-A (2) 2.5 3.0 Detail of Contacts A Detail of Contacts B 2.50 1.0 0.8 ±0.05 Note : All dimensions are in millimeters unless otherwise stated. Rev. 0.1 / May 2008 ...
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PACKAGE OUTLINE 512Mx 72 - HMP351U7MFP8C 4.0±0.1 5.175 63.0 Detail-A (2) 2.5 3.0 Detail of Contacts A Detail of Contacts B 2.50 1.0 0.8 ±0.05 Note : All dimensions are in millimeters unless otherwise stated. Rev. 0.1 / May 2008 ...
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REVISION HISTORY Revision 0.1 Rev. 0.1 / May 2008 1240pin DDR2 SDRAM Unbuffered DIMMs History Initial data sheet released Date May. 2008 21 ...