M25PX80 Numonyx, M25PX80 Datasheet - Page 35

• Manufacturer Part Number: M25PX80
• Description: 8-mbit, Dual I/o, 4-kbyte Subsector Erase, Serial Flash Memory With 75 Mhz Spi Bus Interface
• Manufacturer: Numonyx

6.13
Figure 18. Dual Input Fast Program (DIFP) instruction sequence
1. A23 to A22 are Don't care.
Program OTP instruction (POTP)
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.
The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the
instruction opcode, three address bytes and at least one data byte on Serial Data input
(DQ0).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Program OTP instruction is not executed.
There is no rollover mechanism with the Program OTP (POTP) instruction. This means that
the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,
once all 65 bytes have been latched in, any following byte will be discarded.
The instruction sequence is shown in
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is t
S
C
DQ0
S
C
DQ0
DQ1
DQ1
MSB
6
7
32
DATA IN 1
0
PP
4
5
33
) is initiated. While the Program OTP cycle is in progress, the Status Register
1
2
3
34
2
Instruction
0
1
35 36 37 38 39 40 41 42
MSB
3
6
7
DATA IN 2
4
4
5
5
2
3
High Impedance
6
1
0
7
MSB
6
7
DATA IN 3
23
8
5
4
22 21
Figure
9 10
2
3
24-bit address
0
1
43
19.
MSB
6
7
44 45 46 47
DATA IN 4
3
28 29 30 31
4
5
2
3
2
1
0
1
0
MSB
6
7
DATA IN 5
4
5
2
3
0
1
MSB
DATA IN 256
6
7
4
5
2
3
0
1
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