STPMC1 ST Microelectronics, STPMC1 Datasheet
STPMC1
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STPMC1 Summary of contents
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... This allows the achievement of very high computation precision with fast and efficient digital architecture. All the data recorded by the STPMC1 are accessible through an SPI port, which is also used to configure and calibrate the device. The configuration and calibration data can be saved in a 112-bit OTP block, or dynamically set in microprocessor-based meters ...
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... Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 Theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 General operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.3 Resetting the STPMC1 (status bit HLT 9.4 Clock generator (bits MDIV, FR1, HSA 9.5 Zero crossing detection (signal ZCR 9.6 Period and line voltage measurement (status bits: LIN, BFR, LOW, BFF) 24 9.7 Single wire operation mode: SWM (status bits: NAH, BFR, configuration bit FRS) ...
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... Group 2 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Group 3 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Group 4 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Group 5 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Group 6 data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Parity calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Remote reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Reading data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Writing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Interfacing the standard 3-wire SPI with STPMC1 SPI . . . . . . . . . . . . . 63 Permanent writing of the CFG bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Doc ID 15728 Rev 1 Contents 3/76 ...
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... Contents www.DataSheet4U.com 10.3 Voltage and current RMS values calculation . . . . . . . . . . . . . . . . . . . . . . 69 10.4 Energy integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.5 Fundamental power calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4/76 Doc ID 15728 Rev 1 STPMC1 ...
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... STPMC1 www.DataSheet4U.com List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Thermal data Table 5. Programmable pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Input channels from the STPMSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10. Frequency settings through MDIV and FR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 11 ...
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... List of figures www.DataSheet4U.com List of figures Figure 1. STPMC1 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. Pin connections (top view Figure 3. Application schematic in standalone operating mode Figure 4. Application schematic using an MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Supply current vs. supply voltage, T Figure 6. Digital voltage regulator: line - load regulation µF across V Figure 7 ...
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... STPMC1 www.DataSheet4U.com 1 Functional block diagram Figure 1. STPMC1 device block diagram VCC VCC Linear Vregs Linear Vregs Band Gap Band Gap XTAL1 XTAL1 XTAL2 XTAL2 CLK CLK DAx-C DAx DAx DAx DAx-V DAx DAN-C DAN DAN DAN DAN-V DAN-V ...
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... Programmable input/output pin, see D O Programmable output pin, see Doc ID 15728 Rev 1 LED LED SDATD SDATD SCLNLC SCLNLC XTAL1 XTAL1 XTAL2 XTAL2 SYN SYN V V SSA SSA CLK CLK DAN DAN DAT DAT Name and function Table 5 Table 5 signals Table 5 Table 5 Table 5 Table 5 STPMC1 ...
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... STPMC1 www.DataSheet4U.com 3 Maximum ratings Absolute maximum ratings (see Note:) Table 3. Symbol V DC input voltage CC I Current on any pin (sink/source) PIN V Input voltage at all pins ID V Input voltage at OTP pin OTP ESD Human body model (all pins) T Operating ambient temperature OP T Junction temperature ...
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... SCLNLC No load indicator SDATD Tamper indicator SYN-NP Negative power indicator SCS SPI data transmission enable 10/76 Standalone mode (APL = Doc ID 15728 Rev 1 STPMC1 Peripheral mode (APL = Watchdog reset ZCR signal Programmable energy pulsed output SPI interface ...
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... VSSA Zero Zero Watchdog Watchdog Crossing Crossing VOTP VOTP MON MON MOP MOP LED LED SCS SCS SYN-NP SYN-NP STPMC1 STPMC1 SCL-NC SCL-NC SDA-TD SDA-TD VDD VDD XTAL1 XTAL1 XTAL2 XTAL2 VSS VSS VSSA VSSA Pulsed Pulsed Output Output Energy Energy ...
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... Interface S-phase voltage, current Interface T-phase voltage, current Interface PTAT, neutral current Interface PTAT or hall Low-end user interface Note: The components listed above refer to a typical metering application. In any case, STPMC1 operation is not limited to the choice of these external components. 12/76 Component Value Microprocessor --- 4 ...
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... STPMC1 www.DataSheet4U.com 6 Electrical characteristics ( unless otherwise specified) Table 7. Electrical characteristics Symbol Parameter Energy measurement accuracy f Effective bandwidth BW General Section V Operating supply voltage CC Supply current. Configuration I registers cleared or device CC locked Increase of supply current per I configuration bit, during CC programming POR Power on reset on V ...
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... Note: Typical value, not production tested. 14/76 Test conditions Min. 1.2 V =5.3V CC 4.000 8.000 see Table 10 8.000 HSA = 0 HSA = 25° 25°C A Doc ID 15728 Rev 1 STPMC1 Typ. Max. Unit V 0 µ 4.194 4.915 MHz 8.192 9.830 8.192 9.830 MHz ...
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... STPMC1 www.DataSheet4U.com 7 Terminology 7.1 Measurement error The error associated with the energy measured by the STPMC1 is defined as: 7.2 Conventions The lowest analog and digital power supply voltage is called V system ground (GND). All voltage specifications for digital input/output pins are referred to GND. Positive currents flow into a pin. “Sinking current” is the current flowing into the pin, and positive. “ ...
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... Active energy fundamental Reactive energy full bandwidth Reactive energy fundamental X energy type per Y phase Σ for 3-phase Pin names are UPPERCASE Configuration bit names are UNDERLINED Internal signals and status bits are in ITALICS Doc ID 15728 Rev 1 Description STPMC1 ...
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... STPMC1 www.DataSheet4U.com 8 Typical performance characteristics Figure 5. Supply current vs. supply voltage, T 7,5 7,5 6,5 6,5 5,5 5,5 4,5 4,5 Figure 6. Digital voltage regulator: line - load regulation µF across V 2,5 2 1,5 1 0,5 0 -0,5 -0,5 = 25° 3,5 3 4,5 4 (V) ( and °C) DD SSA ...
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... Typical performance characteristics www.DataSheet4U.com Figure 7. Gain response of decimator 18/76 Flat band (10Hz – 300Hz) Flat band (10Hz – 300Hz) Flat band (10Hz Flat band (10Hz 3 dB band (4Hz –700Hz band (4Hz –700Hz band (4Hz 3 dB band (4Hz Doc ID 15728 Rev 1 STPMC1 ...
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... Theory of operation 9.1 General operation The STPMC1 (also called a calculator ASSP designed for effective measurement in power line systems utilizing the Rogowski coil, current transformer, Shunt or Hall current sensors. This device, used with the STMicroelectronics STPMSx companion chip (an analog front-end device), can be implemented as standalone peripheral in a microprocessor based 1 3-phase energy meter ...
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... When the DAH input stream is selected checked to detect an external magnetic influence (EMI) to the meter. 20/76 Table 31), the user can select either the voltage stream of the Doc ID 15728 Rev 1 STPMC1 ...
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... The STPMC1 contains a power on reset (POR) detection circuit. If the V than 2.5 V then the STPMC1 goes into an inactive state, all the functions are blocked asserting a reset condition. This is useful to ensure correct device operation at power-up and during power-down. The power supply monitor has built-in hysteresis and filtering, which gives a high degree of immunity from false triggering due to noisy supplies. A bandgap voltage reference (VBG) of 1.23 V ± ...
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... During the device reset, the status bit HLT is held high, meaning that data read from the device register are not valid. 9.4 Clock generator (bits MDIV, FR1, HSA) All the internal timing of the STPMC1 is based on the XTAL1 signal. This signal can be generated in two different ways: ● Quartz: the oscillator works with an external crystal. ...
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... The ZCR signal is a 3-phase voltage zero cross signal the result of a XNOR of the ZCR of each phase. The ZCR of each of the three-phases is a 100 Hz signal 3-phase ZCR is 300 Hz signal. The ZCR signal is available on the MOP pin only when the STPMC1 works as a peripheral with the configuration bit APL=0. ...
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... LIN is higher than the MCLK Table /8 pulses between two trailing edges of LIN is lower than the MCLK Doc ID 15728 Rev 1 /8 reference signal, measures the MCLK MCLK 18 /2 freq. max MCLK 128.0 Hz 150.0 Hz 125.0 Hz 150.0 Hz 30). Figure STPMC1 16 /2 MCLK 10. ...
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... Single wire operation mode: SWM (status bits: NAH, BFR, 9.7 configuration bit FRS) The STPMC1 supports single wire meter (SWM) operation. In this condition, since there is no voltage information, the current RMS values, instead of the energies, are accumulated in 20-bit dedicated registers located in ACR, ACS, ACT (20-bit accumulator of RMS I [Ah]) ...
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... Usually the supply voltage for the electronic meter is taken from the line voltage. In SWM, since the line voltage is not present anymore, some other power source must be used in order to provide the necessary supply to STPMC1 and the other electronic components of the meter. Load monitoring (status bit BIL, configuration bit LTCH) 9 ...
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... V. In NLC function is also implemented an hysteresis. When the current is falling the threshold is half lower than that described above. Error detection (status bits: BCF, PIN) 9.9 The STPMC1 has two error detection circuits that checks: ● the ● the state of output pins The first error detection circuit checks if any of the within the period of observation (250 µ ...
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... Tamper detection through bit BCS is meaningful only for SYS = (systems with neutral wire). In other measurement systems it is not useful because there are not enough input current streams. The STPMC1 check tamper detection only if 28/ indicates only BCS or EMI. ...
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... STPMC1 www.DataSheet4U.com Where max Bit BCS is set according to Table 14. Tamper conditions BCS 0 1 with ( RMS Phase sequence is wrong (status bit BSF) 9.10.2 One tamper condition is that phase sequence is not correct. A 3-ph phase status bit BSF checks the sequence of phases, which three phase system is one of the following: ● ...
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... SIGN = 0, SIGN = 0 BIF = SIGN = 1, SIGN = 0 BIF = MAX 16 = RMS = 2 with hysteresis. MAX Doc ID 15728 Rev 1 and i represent the voltage and the /16 /16 MAX STPMC1 ...
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... Energy to frequency conversion (configuration bits: APL, KMOT, LVS, FUND) The STPMC1 provides energy to frequency conversion both for calibration and energy readout purposes. The three hard-wired xDSP, implemented as four 2-channel calculations and produce output data and signals. Inside them, each three stage decimation filter inputs a filtered RMS computer ...
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... APL, KMOT, LVS, FUND) The higher flexibility of the STPMC1 allows its use in microcontroller based energy meters. In this case the STPMC1 must be programmed to work in peripheral mode setting bit APL [ All the SPI pins (SCS, SCLNCL, SDATD, SYN) are used only for communication purposes, allowing the microcontroller to write and read the internal STPMC1 registers ...
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... STPMC1 www.DataSheet4U.com Table 17. LED pin configuration for APL = 0 LVS (1 bit) FUND (1 bit) KMOT (2 bits the number of pulses per kWh set with calibration. APL = 1: MOP/MON provides stepper motor driving signals from 3-phase active energy wide band register with frequency CM related to C (number of pulses on LED pin, see par. ...
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... Driving a stepper motor - standalone operating mode (configuration bits: APL, LVS, KMOT) When used in standalone mode (APL[1] = 1), the STPMC1 is able to directly drive a stepper motor. From signal P (3-ph active energy), stepper motor driving signals MA and MB (see Figure 11 ) are generated by means of internal divider, mono-flop and decoder and brought to MOP and MON pins ...
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... Ferraris mode Absolute accumulation per 1 phase 2 Ferraris mode per phase 3 Signed accumulation 9.15 Phase delay calculation The STPMC1 allows the calculation of the phase delays between voltages. If the line frequency f KMOT (2 bits) LED energy output - Active energy wide band Active energy wide band depends upon phase X power direction ...
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... ST TR ⎝ ⎛ ⎜ time t t Art 10 Art RS ST ⎝ , Equation 2 and Equation 3 f MCLK Doc ID 15728 Rev 1 ⎞ 8 Asr 12 11 ⎟ ⎠ f MCLK ⎞ 8 Art 12 11 ⎟ ⎠ f MCLK it is possible to retrieve phase delays MHz STPMC1 , ...
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... STPMC1 www.DataSheet4U.com LINE ACR[7:0] = 0101 1010 ACS[7:0] = 0010 0000 ACT[7:0] = 0000 0101 Asr[12 Asr[10:0] = 000 0101 0010 Art[12 Art[10:0] = 00001011010 time Asr 82 s ⇒ time Art 90 s ⇒ Example 9: Phase delay calculation MHz; MDIV = 0; FR1 = 0 XTAL1 ...
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... Phase compensation The STPMC1 does not introduce any phase shift between voltage and current channel. However, the voltage and current signals come from transducers, which could have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT) ...
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... STPMC1 www.DataSheet4U.com Equation 4 is the phase compensation in degree, phc K is the calculated coefficient, PHC f is the frequency of voltage signal, line f is the clock for phase compensation. phc The clock for phase compensation f Table 22. Table 23. Example 10: Phase compensation for TCS = 0 Phase shift current for - ...
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... CPC[0] CpC[1] CpC[ CPC[0] CpC[ STPMC1 φ phc 0.034° 0.029° 0.018° 0.015° 0.017° 0.015° 0.009° 0.007° 64 ...
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... STPMC1 www.DataSheet4U.com (32 CpC[ CPC[0] + CPX[3:0]) phc Table 25. CLK 4.194 MHz 4.195 MHz 8.192 MHz 9.830 MHz 4.194 MHz 4.195 MHz 8.192 MHz 9.830 MHz Example 12: Phase compensation for Phase shift current for - CPC[ CPX[ (32 CpC[1: CPC[0] + CPX[3:0]) ...
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... CCA 8 1 CCA 8192 CCA 8 1 CCB 8192 and these values are subtracted from neutral and phase currents S - CCA 8 1 CCA 8192 CCA 7 1 CCB 8192 Doc ID 15728 Rev 1 STPMC1 (alpha) and (beta), are ( 3 3.1 %) and 0. 0.39 %) ...
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... STPMC1 www.DataSheet4U.com Equation 9 From these factors matrix, shown in compensation multiplying each phase and neutral current with its row, adding the products together and subtracting them from the currents. Table 28. Mutual current compensation matrix for three-phase systems (SYS < 4) phase ...
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... T f MCLK Doc ID 15728 Rev 1 STPMC1 8 bit 8 bit 8 bit 8 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 3-ph lower status 3-ph lower status 3-ph lower status 3-ph lower status 3-ph up status 3-ph up status 3-ph up status ...
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... STPMC1 www.DataSheet4U.com 9.17.2 Group 1 data records Figure 14. Group 1 data records parity parity parity parity parity parity DMR DMR DMR DMR DMS DMS DMS DMS parity parity parity parity parity parity DMT DMT DMT DMT parity parity parity parity parity parity DMN DMN ...
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... RMS uN RMS uN RMS uN RMS uN RMS uN RMS uN RMS 12 bit 12 bit 12 bit 12 bit 12 bit 12 bit , replace Doc ID 15728 Rev 1 STPMC1 iR RMS iR RMS iR RMS iR RMS iR RMS iR RMS iS RMS iS RMS iS RMS iS RMS iS RMS iS RMS iT RMS iT RMS iT RMS iT RMS iT RMS iT RMS iN RMS iN RMS ...
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... STPMC1 www.DataSheet4U.com 9.17.4 Group 3 data records Figure 16. Group 3 data records parity parity parity parity parity parity DAR DAR DAR DAR DAS DAS DAS DAS parity parity parity parity parity parity DAT DAT DAT DAT parity parity parity parity parity parity CF0 CF0 ...
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... Table 30 ). Bit [0] ( BIL ) represents no-load Table 30 ). Bit [0] ( BIL ) represents no-load Table 30 ). Bit [0] ( BIL ) represents no-load Table 31 ) Doc ID 15728 Rev 1 STPMC1 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit R-phase status R-phase status R-phase status R-phase status R-phase status R-phase status ...
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... STPMC1 www.DataSheet4U.com 9.17.6 Group 5 data records Figure 18. Group 5 data records parity parity parity parity parity parity DFR DFR DFR DFR DFS DFS DFS DFS parity parity parity parity parity parity DFT DFT DFT DFT parity parity parity parity parity parity CF2 CF2 ...
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... Doc ID 15728 Rev 1 STPMC1 8 bit 8 bit 8 bit 8 bit 8 bit 8 bit R-phase elapsed ...
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... FB prty &= 0xF0 = F0 9.18 Status bits map The STPMC1 includes 12 status bits for 3-phase cumulative, and 3 8-bit status byte, one per each phase. All of them provide information about the current meter status. Table 29. 3-phase status bits description Bit Name ...
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... SYN pin and Tamper flag (is the OR of all tamper conditions - see paragraph SDATD pin. All the other signals can be read only through SPI interface. When STPMC1 is used in peripheral mode all these signals can be read through the SPI interface. See paragraph records ...
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... OTP bit. There is also a special high voltage input pad VOTP, which delivers the power level necessary for permanent write to OTP cell. The STPMC1 can work either using the data stored in the OTP cells or the data from the shadow latches. This is done through the RD system signal (see paragraph set, the CFG bits originates from corresponding OTP shadow latches otherwise cleared, the CFG bits originates from corresponding OTP antifuses ...
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... SYS=6: 1-phase, 2-wire __TN, 2-system _ST_ (tamper coil:shunt) - SYS=7: 1-phase, 2-wire __TN, 1-system __T_ Polarity of SCLNLC idle state selection: - SCLP=0: idle state SCLNLC= SCLP=1: idle state SCLNLC=0 Doc ID 15728 Rev 1 Description KMOT=2 KMOT=3 S phase T phase KMOT=2 KMOT=3 P/32 P/256 KMOT=2 KMOT=3 P/320 P/2560 STPMC1 ...
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... STPMC1 www.DataSheet4U.com Table 31. Configuration bits map (continued) Address Name 7-BIT DEC Binary 0010101 21 0010110 22 FR1 0010111 23 0011000 24 0011001 25 0011010 26 0011011 27 CCA 0011100 28 0011101 29 0011110 30 0011111 31 0100000 32 0100001 33 0100010 34 0100011 35 0100100 36 0100101 37 0100110 38 0100111 39 0101000 40 0101001 41 0101010 42 0101011 43 0101100 44 0101101 45 0101110 46 0101111 ...
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... Compensation of phase error of phase T - PM=0, TCS=0: Mutual current influence compensation data B SYS = SYS = CCB[7..3] = CCB[7..0] = CCB[2.. PM=1: Calibration extenders for current 8 CCB[7..6] = CiT CCB[5..4] = CiS CCB[3..2] = CiR CCB[1..0] = CiN 2 Common sign and coarse phase error compensation Doc ID 15728 Rev 1 STPMC1 Description ...
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... STPMC1. The mode signals are not retained when the STPMC1 supply is not available and then they are cleared when a POR occurs, while they are not cleared when a remote reset command (RRR) is sent through SPI ...
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... SYN pin status select if the SPI is in read (SYN = 1) or write mode (SYN = 0). When SCS is high and SYN is also high the results of the input or output data are transferred to the transmission latches. 58/76 supply voltage of the STPMC1 to generate the VOTP voltage ( while a low level signal means a voltage value lower than 0. ...
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... SCS, SCLNLC and SDATD are in a logic high state. Any SPI operations should start from such an idle state. The exception to this rule is when the STPMC1 has been put into standalone application mode. In this mode it is possible that the states of the pins SCLNLC, SDATD and SYN are not high due to the states of the corresponding internal status bits ...
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... Internal data transferred to SDATD SDATD data is stable and can be read 8 60/76 f(read) f(read) 1st byte 1st byte CLK Doc ID 15728 Rev 1 STPMC1 last bit of 32nd byte last bit of 32nd byte ...
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... In order to change the state of a latch one must send to the STPMC1 a byte of data which is the normal way to send data via SPI. This byte consists of 1-bit data to be latched (msb), followed by 7-bit address of destination latch, which makes total 8 bits of command byte, as summarized in the table below ...
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... Commands for changing system signals should be sent during active signals SCS and SYN shown in driver of STPMC1 and make the SDATD as an input pin. A string of commands can be send within one period of active signals SCS and SYN or command can be followed by reading the data record but, in this case, the SYN should be deactivated in order to enable SDATD output driver and a SYN pulse should be applied before activation of SCS in order to latch the data ...
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... Interfacing the standard 3-wire SPI with STPMC1 SPI Due to the fact that a 2-wire SPI is implemented in the STPMC1 clear that sending any command from a standard 3-wire SPI would require 3-wire to 2-wire interface, which should produce a proper signal on SDATD from host signals SDI, SDO and SYN. A single gate 3- state buffer could be omitted by an emulation of SPI just to send some command ...
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... SCS because the idle state of SCS would make the signal TSTD immediately effective which in turn, would abort the procedure and possibly destroy the device due to clearing of system signal RD and so, connecting all gates NMOS sense amplifiers of already permanently set CFG bits to the VOTP source. 64/76 Doc ID 15728 Rev 1 STPMC1 ...
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... STPMC1 www.DataSheet4U.com 10 Energy calculation algorithm For the purpose of simplicity the energy computation shown below is relative to only one phase. Given line voltage and current as: Equation sin ( t) The voltage divider, AD converter and calibrator produce the value: Equation /( The Rogowski coil preamplifier, AD converter and calibrator produce the value: ...
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... Equation 23 ), yielding: sin ( t) sin ( ABk INT cos ( t) cos ( ABk INT Doc ID 15728 Rev 1 Equation 12 or Equation multiplied to the or Equation 24 ) and current stream from the [cos - cos ( INT [cos + cos ( INT STPMC1 nd stage of ...
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... STPMC1 www.DataSheet4U.com In case of a non Rogowski sensor, the corresponding products are: Equation Equation Then a subtraction of P Equation where: Equation This gives the same result for P in case of non Rogowski sensor, substituting B and k ...
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... Equation 17 nd stage ( Equation 15 [sin - sin ( INT [sin + sin ( INT + sin ( sin (2 Ik sin ) sin L INT RMS RMS I sin k RMS RMS P Equation 45 ), the 16-bit current from the STPMC1 or Equation or Equation INT st nd ...
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... STPMC1 www.DataSheet4U.com 10.3 Voltage and current RMS values calculation The I value is produced from 16-bit value of RMS Equation RMS L INT The Ui RMS Equation RMS D In case of non Rogowski sensor, the same dedicated RMS blocks produce some other values, because input values for the blocks are changed. ...
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... AC [cos DIF INT ) / cos ( Doc ID 15728 Rev 1 [cos + cos ( INT [cos - cos ( INT cos ) cos L INT RMS RMS - cos ( cos ( cos ( RMS RMS STPMC1 k P cos ( ...
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... STPMC1 www.DataSheet4U.com Equation uiic iiic Similar results are found in cases of non Rogowski sensors: Equation diic siic / ABk cos ( t) sin ( ABk INT INT / cos ( t) sin ( [sin INT Doc ID 15728 Rev 1 Energy calculation algorithm [sin - sin ( ...
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... Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK specifications, grade definitions and product status are available at: ® ECOPACK 72/76 packages, depending on their level of environmental compliance. ECOPACK trademark. Doc ID 15728 Rev 1 STPMC1 ® www.st.com . ...
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... STPMC1 www.DataSheet4U.com Dim. Min 0.05 A2 0.8 b 0.19 c 0.09 D 6.4 E 6 0° PIN 1 IDENTIFICATION TSSOP20 mechanical data mm. Typ. Max. 1.2 0.15 1 1.05 0.30 0.20 6.5 6.6 6.4 6.6 4.4 4.48 0.65 BSC 8° 0.60 0. Doc ID 15728 Rev 1 Package mechanical data inch. Min. Typ. Max. 0.047 0.002 0.004 0.006 0.031 0.039 0.041 0.007 ...
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... Dim. Min 12 6.8 Bo 6.9 Ko 1.7 Po 3.9 P 11.9 74/76 Tape & reel TSSOP20 mechanical data mm. Typ. Max. 330 13.2 22.4 7 7.1 1.9 4.1 12.1 Doc ID 15728 Rev 1 STPMC1 inch. Min. Typ. Max. 12.992 0.504 0.519 0.795 2.362 0.882 0.268 0.276 0.272 0.280 0.067 0.075 0.153 0.161 0.468 0.476 ...
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... STPMC1 www.DataSheet4U.com 12 Revision history Table 34. Document revision history Date Revision 22-May-2009 1 Initial release. Doc ID 15728 Rev 1 Revision history Changes 75/76 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 76/76 Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 15728 Rev 1 STPMC1 ...