CD2231 Intel Corporation, CD2231 Datasheet - Page 113



Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Intel Corporation
Register Name: CCR
Register Description: Channel Command, Mode 1
Default Value: x’00
Access: Byte Read/Write
Bit 7
Note: Processing CCR commands is a low-priority task for the internal firmware, since they seldom
CCR — Mode 1
The various command and control bits in this register perform largely independent functions. The
host can assert multiple command bits to achieve the desired effect. The CD2231 clears the register
to zero after it accepts and acts on a host command. The host must verify that the contents of this
register are zero prior to issuing a new command. If the RESET ALL command is issued, all other
commands are ignored. All other combinations are legal, and the order of processing is as follows:
occur. The user musttake care when waiting for command completions at critical times, that is,
during interrupt service routines.
Channel Control Commands (Bit 7 = 0)
Bit 7
Bit 6
Bit 5
1. Clear channel
2. Initialize channel
3. Enable receive
4. Disable receive
5. Enable transmit
6. Disable transmit
Bit 6
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
Must be zero.
Clear channel command
When this command is issued, the CD2231 clears the data FIFOs and current trans-
mit and receive status of the channel in the CSR. If the channel is currently transmit-
ting a frame in synchronous protocol, the host should issue the transmit abort
(special transmit command) before issuing a Clear command. The channel parame-
ters are not affected by a Channel Clear command. The Clear Channel command
causes both receive and transmit FIFOs to be cleared, the transmitter and receiver to
be disabled, and all DMA Status registers (DMABSTS, A/BRBSTS and A/BTB-
STS) to be cleared.
Initialize channel
If any change is made to the Protocol Mode Select bits in the CMR (Channel Mode
register) or to the COR1 (Channel Option Register 1), the channel must be reinitial-
ized by this command. The InitCh command causes the internal protocol-specific
registers to be initialized.
Bit 5
Bit 4
Bit 3
Bit 2
Motorola Hex Address: x’13
Bit 1
Intel Hex Address: x’10
Bit 0

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