CD2231 Intel Corporation, CD2231 Datasheet - Page 124
Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Register Name: LICR
Register Description: Local Interrupting Channel
Default Value: C1:C0 contain channel number
Access: Byte Read/Write
Local Interrupting Channel Register (LICR)
These per-channel registers are initialized with each channel number. The locations are RAM
registers and can be used for any purpose.
Modem pin change detect
Master interrupt enable for modem change detect functions. The host can select
which modem pins are watched for input change and select either or both directions
of change by programming the change detect option bits in COR4 and COR5. A
Group1 type interrupt (see LIVR description) is generated from this enable.
Reserved – must be ‘0’.
The receive FIFO threshold has been reached in Interrupt Transfer mode, causing a
Group 3 receive data interrupt. Any receive exception causes a Group 3 receive
General timer(s) timeout
In Synchronous mode, this bit enables a Group 1 interrupt when either timer reaches
Transmitter empty. If enabled, a Group 2 interrupt is generated when the channel is
completely empty of transmit data.
Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer
mode. Group 2 interrupts are generated at the end of transmit DMA buffers or when
the FIFO threshold is reached in Interrupt Transfer mode.
Defines the interrupting channel number
Motorola Hex Address: x’26
Intel Hex Address: x’25