CD2231 Intel Corporation, CD2231 Datasheet - Page 67

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

6.0
6.1
6.1.1
6.1.2
Datasheet
Protocol Processing
HDLC Processing
Frame Check Sequence
The FCS is a 16-bit standard computation used in HDLC, and defined in ISO 3309. This FCS
algorithm is the same that is used with the synchronous HDLC operation of the CD2231. The basic
characteristics of the FCS are the following:
Accumulation: FCS computation starts after the opening flag and continues to the closing flag.
Polynomial: The standard polynomial is
Pre-load: The FCS 16-bit accumulator is pre-set to all ‘1’s.
Transmit order: The FCS bits are identified as X15 to X0. The most-significant bit is X15, and is
transmitted first. Thus, the first FCS character transmitted has bits X15–X8 in character positions
D1–D8, respectively. The second FCS character has bits X7–X0 in character positions D1–D8,
respectively.
Transmit polarity: Inverted.
Correct remainder: The receiver calculates the entire received frame, including the received FCS
field. If the frame is received error free, then the correct remainder in the FCS accumulation is ‘F 0
B 8’ (X15 is the leftmost bit).
The FCS can be individually enabled or disabled for the transmitter and receiver.
If enabled for the transmitter, the device appends the FCS on transmitted frames. If disabled, the
device adds no FCS at the end of the frame.
If enabled for the receiver, the device computes the received FCS and reports the results. If the FCS
append is also enabled, the device includes the 2-byte FCS in the received data presented to the
host. If disabled, the device does not test the received FCS.
HDLC Transmit Mode
The transmitter can be programmed to idle in either Flag (01111110) or Mark (continuous 1’s)
mode by the Idle bit (COR3[3]) in Channel Option Register 3. When idle in Mark mode, frame
transmission can be programmed to be prepended by a programmable number of pad characters
and flags. The pad character can be selected as either 00 or AA. The pad characters allow the
remote receivers phase locked loop to synchronize quickly to the data. When NRZI encoding is
used for Manchester encoding, the 00 character guarantees a transition every bit time, and the AA
character guarantees exactly one transition per bit time.
If the transmitter is idle in Mark mode, frame transmission is started when data is made available to
the transmitter, either by the TDR (Transmit Data register) or a DMA buffer. First, the
programmable number of pad characters are transmitted, then the programmable number of flag
characters. Data characters are then transmitted and a CRC value accumulated using each data
character.
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
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