S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 274
S1D13505
Manufacturer Part Number
S1D13505
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13505.pdf
(566 pages)
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Page 10
Memory Tab
S1D13505
X23A-B-001-04
Memory Type
Access Time
WE# Control
Memory
Performance
Note
The Memory tab contains settings that control the configuration of the DRAM used for the
S1D13505 display buffer.
Memory Configuration
The DRAM memory type and access time determines the optimal memory clock
(MCLK). See “Clocks Tab” on page 12 for an explanation on how to determine the op-
timal memory clock.
Access Time
Memory Type
These four settings must be configured based on the
specification of the DRAM being used. For each of the
following settings refer to the DRAM manufacturer’s
specification unless otherwise noted.
Selects the access time of the DRAM.
The S1D13505 evaluation boards use 50ns DRAM.
Selects the memory type, either Extended Data Out
(EDO) or Fast Page Mode (FPM).
The S1D13505 evaluation boards use EDO DRAM.
Epson Research and Development
13505CFG Configuration Program
Vancouver Design Center
Issue Date: 01/03/29
Installed Memory
Suspend Mode
Refresh Time
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