S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 363
S1D13704
Manufacturer Part Number
S1D13704
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D13704.pdf
(492 pages)
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Vancouver Design Center
4.1.2 Using The Generic #1 Host Bus Interface
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
Issue Date: 01/02/12
Figure 4-2: Typical Implementation of MC68328 to S1D13704 Interface - Generic #1
If UDS and/or LDS are required for their alternate IO functions, then the MC68328 to
S1D13704 interface may be implemented using the S1D13704 Generic #1 host bus
interface. Note that in either case, the DTACK signal must be made available for the
S1D13704, since it inserts a variable number of wait states depending upon CPU/LCD
synchronization and the LCD panel display mode. WAIT# must be inverted (using an
inverter enabled by CS#) to make it an active high signal and thus compatible with the
MC68328 architecture. A single resistor is used to speed up the rise time of the WAIT#
(DTACK) signal when
terminating the bus cycle.
The following diagram shows a typical implementation of the MC68328 to S1D13704
using the Generic #1 host bus interface.
MC68328
DTACK
D[15:0]
RESET
A[15:0]
CSB3
UWE
CLK0
LWE
OE
Vcc
470
WE0#
AB[15:0]
DB[15:0]
WAIT#
RD/WR#
RD#
BUSCLK
WE1#
RESET#
CS#
S1D13704
X26A-G-007-03
S1D13704
Page 13
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