FR65E Fujitsu Microelectronics, Inc., FR65E Datasheet
FR65E
Related parts for FR65E
FR65E Summary of contents
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... This microcontroller is ideal for built-in applications such as DVD players, navigation systems, high-capability FAX and printer control that demand high-capability CPU processing power. The MB91307B is a FR65E series product based on the FR30/40 series CPU with enhanced bus access for higher speed operation. ...
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MB91307B • Instructions for built-in applications: memory-to-memory transfer, bit processing, barrel shift etc. • Instructions adapted for high-level languages: function input/output instructions, register contents multi-load/ store instructions • Easier assembler notation: register interlock function • Built-in multiplier/instruction level support Signed ...
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UART • Full duplex double buffer • 3-channel • Parity/no parity selection • Asynchronous (start-stop synchronized), CLK-synchronized communications selection • Built-in exclusive baud rate timer • External clock can be used as transfer clock • Variety of error detection ...
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MB91307B PIN ASSIGNMENT PA3/CS3 61 PA4/CS4 62 PA5/CS5 PA6/CS6 65 PA7/CS7 66 P80/RDY 67 P81/BGRNT 68 P82/BRQ UUB/WR0 71 P85/ULB/WR1 72 NMI 73 HST INIT 76 P90/SYSCLK 77 P91 78 ...
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PIN DESCRIPTIONS I/O Pin no. Pin name circuit type D16 to D23 P20 to P27 93 to 100 D24 to D31 C 102 to 109 A00 to A07 F 111 to 118 A08 to A15 F ...
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MB91307B I/O Pin no. Pin name circuit type SC0 27 F PI2 SI1 28 F PI3 SO1 29 F PI4 SC1 30 F PI5 SI2 31 F PH0 SO2 32 F PH1 SC2 33 F PH2 TOT0 35 C PH3 ...
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I/O Pin no. Pin name circuit type SDA 38 Q PH6 SCL 39 Q PH7 DREQ2 40 F PG0 DACK2 41 F PG1 DEOP2 DSTP2 42 F PG2 MD2 to MD0 G DREQ0 46 F PB0 DACK0 ...
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MB91307B I/O Pin no. Pin name circuit type DREQ1 49 F PB3 DACK1 50 F PB4 DEOP1 DSTP1 51 F PB5 IOWR 56 F PB6 IORD 57 F PB7 CS0 58 F PA1 CS1 59 ...
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I/O Pin no. Pin name circuit type CS4 62 F PA4 CS5 63 F PA5 64 C CS6 65 F PA6 CS7 66 F PA7 RDY 67 C P80 BGRNT 68 F P81 BRQ 69 P P82 ...
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MB91307B (Continued) I/O Pin no. Pin name circuit type 73 NMI H 74 HST H 76 INIT B SYSCLK 77 F P90 78 P91 F MCLK 79 F P92 80 P93 LBA F P94 BAA 82 P95 ...
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I/O CIRCUIT TYPE Type STANDBY CONTROL B C STANDBY CONTROL D CONTROL Circuit clock input digital input digital output digital output digital input analog input MB91307B Remarks • Oscillator feedback resistance approx • CMOS hysteresis ...
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MB91307B Type F STANDBY CONTROL Circuit digital output digital output digital input digital input digital input digital output digital output digital input digital output digital output Remarks • CMOS level output CMOS level hysteresis input ...
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Type P STANDBY CONTROL Q STANDBY CONTROL Circuit digital output digital output CONTROL digital input Open drain control digital output digital input MB91307B Remarks • CMOS level input/output with standby control with pull-down resistance ( • Open ...
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MB91307B HANDLING DEVICES MB91307 Series • Preventing Latchup When CMOS integrated circuit devices are subjected to applied voltages higher than V (other than medium- and high-withstand voltage pins voltages lower than V in excess of rated levels are ...
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Hardware standby at power-on startup If a power-on startup is followed immediately by a hardware standby request, the reset initialization of settings (INIT) from the INIT pin has priority. However in case of transition from the reset initialization (INIT) ...
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MB91307B • Precautions for use of stop mode The built-in regulator in this device stops operating when the device is in stop mode. In such cases as when increased leak current ( stop mode, or abnormal operation or ...
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Notes on the PS register Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt handler to break or the PS flag to update its display setting when the debugger is being used. As ...
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... MB91307B BLOCK DIAGRAM Bit search RAM 128 KB Clock control Interrupt controller External interrupt 18 FR65E CPU Core 32 Instruction cache Bus Converter DMAC External memory Adapter interface 16 UART U-TIMER Reload A/D timer 3- Port ...
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CPU AND CONTROL BLOCK Internal Architecture The FR series CPU is a high-performance core using RISC architecture with a high-capability instruction set intended for built-in applications. 1. Features • Uses of RISC Architecture Basic instruction set: 1 instruction to 1 ...
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MB91307B 2. Internal Architecture The FR series CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction bus (I-BUS) is connected to an on-chip instruction cache. a 32-bit bus (F-BUS) to provide an interface between the ...
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Programming Model Basic Programming Model General-purpose register Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplier result registers 32 bits R0 R1 R12 AC R13 R14 FP R15 ILM ...
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MB91307B 4. Registers General Purpose Register R0 R1 R12 R13 R14 R15 Registers are general-purpose registers. These registers can be used as accumulators for compu- tation operations pointers for memory access. Of the ...
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SCR (System Condition code Register) Stepwise division flags These flags store interim data during execution of stepwise division. Step trace trap flag Indicates whether the step trace trap is enabled or disabled. The step trace trap function is used by ...
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MB91307B RP (Return Pointer The return register stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of ...
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SETTING MODE In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating mode. 1. Mode Pins The three pins MD2, MD1, MD0 are used in mode vector fetch instructions, ...
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MB91307B MEMORY SPACE 1. Memory Space The FR family has addresses) of logical address space with linear access from the CPU. Direct Addressing Areas The following areas of address space are used for I/O operations. These ...
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Use of Built-in RAM The MB91307B provides 128 KB of built-in RAM. To enable use of this RAM, the mode register must be set to internal ROM external bus mode (ROMA=1). Precautions for use of this model • The reset ...
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MB91307B USER PROGRAM INITIALIZATION The following sequence describes an example using built-in RAM. 1. Hardware Setting Conditions MB91307B CS0 A19-1 1) Assume that external ROM is placed beginning at 0010_0000 in the linker. (The following description can ...
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User Program Initialization Steps MB91307B CS0 1) Set the TBR register so that the interrupt table is 001F_FFXX includes a chip select setting, and at the same time the CS0 address is set to be valid at 001X_XXXX CS0 ...
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MB91307B I/O MAP This map shows the correlation between areas of memory space and individual registers in peripheral resources. [How to read the map] Address 0 PDR0 [R/W] PDR1 [R/W] 000000 H XXXXXXXX XXXXXXXX Read/write attributes Register default value after ...
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Address 0 1 000000 H 000004 H PDR8 [R/W] PDR9 [R/W] 000008 H --X--XXX XXXXXXX- 00000C H PDRG [R/W] PDRH [R/W] 000010 H -----XXX XXX00XXX 000018 H to 00001C H 000020 H to 00003C H EIRR [R/W] ENIR [R/W] 000040 ...
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MB91307B Address 0 UTIM [R] (UTIMR [W] ) 00006C H 00000000 00000000 SSR [R/W] SIDR [R/W] 000070 H 00001-00 XXXXXXXX UTIM [R] (UTIMR [W] ) 000074 H 00000000 00000000 ADCR 000078 H ------XX XXXXXXXX 00007C H 000080 H 000084 H ...
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Address 0 1 DMACA0 [R/W] 000200 H 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 000204 H 00000000 00000000 00000000 00000000 DMACA1 [R/W] 000208 H 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00020C H 00000000 00000000 00000000 00000000 DMACA2 [R/W] 000210 H 00000000 ...
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MB91307B Address 0 000300 H 000304 H 000308 H to 0003E0 H 0003E4 H 0003E8 H to 0003EC H 0003F0 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FC H XXXXXXXX ...
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Address 0 1 ICR00 [R/W] ICR01 [R/W] 000440 H ---11111 ---11111 ICR04 [R/W] ICR05 [R/W] 000444 H ---11111 ---11111 ICR08 [R/W] ICR09 [R/W] 000448 H ---11111 ---11111 ICR12 [R/W] ICR13 [R/W] 00044C H ---11111 ---11111 ICR16 [R/W] ICR17 [R/W] ...
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MB91307B Address 0 000600 H 000604 H DDR8 [R/W] DDR9 [R/W] 000608 H --0--000 00000000 00060C H 000610 H 000614 H PFR8 [R/W] PFR9 [R/W] 000618 H --1--0-- 1111111- PFRB2 [R/W] 00061C H 00------ 000620 H 000624 H 000628 H ...
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Address 0 1 ASR6 [R/W] 000658 H XXXXXXXX XXXXXXXX ASR7 [R/W] 00065C H XXXXXXXX XXXXXXXX AWR0 [R/W] 000660 H 011111111 11111111 AWR2 [R/W] 000664 H XXXXXXXX XXXXXXXX AWR4 [R/W] 000668 H XXXXXXXX XXXXXXXX AWR6 [R/W] 00066C H XXXXXXXX XXXXXXXX 000670 ...
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MB91307B Address 0 ECNT0 [W] ECNT1 [W] 000B08 H XXXXXXXX XXXXXXXX EWPT [R] 000B0C H 00000000 00000000 EDTR0 [W] 000B10 H XXXXXXXX XXXXXXXX 000B14 H to 000B1C H 000B20 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B24 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ...
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Address 0 1 000B54 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 [W] 000B58 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 [W] 000B5C H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 [W] 000B60 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1/EODM1 [W] 000B64 H XXXXXXXX XXXXXXXX ...
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MB91307B INTERRUPT SOURCES AND INTERRUPT VECTORS Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request ...
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Interrupt source DMAC1(end, error) DMAC2(end, error) DMAC3(end, error) DMAC4(end, error) A System reserved System reserved System reserved System reserved U-TIMER0 U-TIMER1 U-TIMER2 Time base timer overflow System reserved System reserved System reserved System reserved System reserved System ...
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MB91307B (Continued) Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instructions 42 Interrupt number Interrupt level Offset TBR default address RN ...
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PERIPHERAL RESOURCES 1. Interrupt Controller (1) Overview The interrupt controller receives and processes arbitration of interrupts. Hardware Configuration This module is configured from the following elements. • ICR register • Interrupt priority determination circuit • Interrupt level and interrupt number ...
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MB91307B (2) Register List bit 7 Address : 00000440 H Address : 00000441 H Address : 00000442 H Address : 00000443 H Address : 00000444 H Address : 00000445 H Address : 00000446 H Address : 00000447 H Address : ...
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Address : 00000460 H Address : 00000461 H Address : 00000462 H Address : 00000463 H Address : 00000464 H Address : 00000465 H Address : 00000466 H Address : 00000467 H Address : 00000468 H Address ...
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MB91307B (3) Block Diagram RI00 RI47 (DLYIRQ) 46 (“1” when LEVEL UNMI WAKEUP Determine order of priority 5 NMI processing LEVEL LEVEL, determination VECTOR ICR00 generation 6 VECTOR determination ICR47 R-BUS 11111) LEVEL4 0 HLDREQ MHALTI hold request VCT5 0 ...
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External Interrupt - NMI Control Block (1) Overview The External Interrupt - control block controls external interrupt requests input at the NMI and INT0-7 pins. The request level can be selected from “H,” “L,” “rising edge,” or “falling edge” ...
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MB91307B 3. REALOS Related Hardware REALOS related hardware is used by the REALOS operating system. Therefore, when REALOS is in use, these resources cannot be used by user programs. 1) Delay Interrupt Module (1) Overview The delay interrupt module is ...
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Bit Search Module (1) Overview Searches data written to input registers for “0” or “1” or change points, and outputs the value of the detected bits. (2) Register List 31 Address : 000003F0 H Address : 000003F4 H Address ...
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MB91307B 4. 16-bit Reload Timer (1) Overview The 16-bit timer is configured from a 16-bit down-counter, 16-bit reload register, prescaler for internal count clock generation, and a control register. For the input clock signal, a selection of three internal clock ...
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Block Diagram 16-bit down counter 16 Clock selector Internal clock 3 16-bit reload register Reload 2 OUT GATE CTL. 2 CSL1 CSL0 Re-trigger IN CTL. EXCK 3 ...
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MB91307B 5. U-TIMER (16 bit timer for UART baud rate generation) (1) Overview The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set using the combination of chip ...
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UART (1) Overview The UART is an I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission, providing the following features. This device features a 3-channel built-in UART. • Full duplex double buffer • Asynchronous (start-stop synchronized) or CLK ...
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MB91307B (3) Block Diagram Control signal From U-TIMER Clock select circuit External clock SC SI (receiving data) Receiving status decision circuit DMA receiving error signal (to DMAC) SMR register 54 TX clock RX clock RX control circuit Start bit detect ...
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A/D Converter (Sequential comparison type) (1) Overview This A/D converter is a module that coverts analog input voltages to digital values, and provides the following features. • Minimum conversion time 5.4 s/ch (at machine clock 33 MHz - CKLP) ...
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MB91307B (3) Block Diagram Sample & hold circuit Channel decoder Timing generator Clock (CLKP) ATG (External pin trigger) Reload timer ch1 (Internal connection) Precautions for Use: When the A/D converter is started from an external trigger or internal timer, the ...
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Interface (1) Overview The interface operates as a master/slave device on the I following features are provided. • Master/slave sending and receiving • Arbitration function • Clock synchronization function • Slave address/general call ...
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MB91307B (Continued) • 10-Bit Slave Address Mask Register (ITMK) Address : 000098 H Default value Address : 000099 H Default value • 7-Bit Slave Address Register (ISBA) Address : 00009B H Default value • 7-Bit Slave Address Mask Register (ISMK) ...
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Block Diagram ICCR I EN IDBL DBL ICCR CS4 CS3 CS2 CS1 CS0 IBSR Bus busy BB Repeat start RSC Last Bit LRB TRX ADT AL IBCR BER BEIE INTE INT IBCR Start SCC Master MSS ACK OK ACK ...
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MB91307B 9. DMAC (DMA Controller) (1) Overview This module is used to accomplish DMA (Direct Memory Access) transfer on FR family devices. DMA transfer controlled by this module increases system performance by enabling high speed transfer of many types of ...
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Register Descriptions ch.0 Control/status register A ch.0 Control/status register B ch.1 Control/status register A ch.1 Control/status register B ch.2 Control/status register A ch.2 Control/status register B ch.3 Control/status register A ch.3 Control/status register B ch.4 Control/status register A ch.4 ...
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MB91307B (3) Block Diagram DMA transfer request to bus controller Read/write Read control Write DDNO To bus controller Write back Access address Write back 62 Counter DMA start Buffer source selection circuit & request Selector acceptance control DTC two-stage register ...
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External Interface (1) Overview The external interface controller controls the interface between the LSI’s internal bus and external memory devices. This section describes the functions of the external interface. (2) Features • bit-length ...
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MB91307B (3) Block Diagram Internal Internal data address bus bus 32 32 write buffer read buffer address buffer (4) I/O Pins These are the external interface pins. (Some pins have dual functions.) < Normal bus interface > A24 to A0, ...
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DMA interface > IOWR, IORD DACK0, DACK1, DACK2 DREQ0, DREQ1, DREQ2 DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2 (5) Register List Address 00000640 00000644 00000648 0000064C 00000650 00000654 00000658 0000065C 00000660 00000664 00000668 0000066C 00000670 00000674 00000678 0000067C 00000680 00000684 00000688 0000068C 000007F8 ...
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MB91307B ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Supply voltage Analog supply voltage Analog reference voltage Input voltage Analog pin input voltage Output voltage Maximum clamp current Total maximum clamp current L level maximum output current L level average output ...
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Note that signal is input when the microcontroller power supply is off (not fixed the power supply is provided from the pins, so that incomplete operation may result. Note that if the B ...
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MB91307B 3. DC Characteristics Parameter Symbol Pin name V See note * IH “H” level input Input pins voltage V HIS other than * V See note * IL “L” level input voltage Input pins V ILS other than * ...
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AC Characteristics (1) Clock Timing Standards Parameter Clock frequency (1) Clock cycle time Clock frequency (2) Clock frequency (3) Clock cycle time Input clock pulse width Input clock rise, fall time Internal operating clock frequency Internal operating clock cycle ...
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MB91307B Clock timing measurement conditions Warranted operating range V (V) CC 1.95 1.65 0 0.78 External/internal clock setting range (MHz CPT f CPP 33 16 Notes ...
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Clock Output Timing Parameter Symbol Cycle time t MCLK, SYSCLK CYC MCLK MCLK t MCLK, SYSCLK CHCL SYSCLK SYSCLK MCLK MCLK t MCLK, SYSCLK CLCL SYSCLK SYSCLK V OH MCLK, SYSCLK * represents the frequency of one ...
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MB91307B (4) Normal Bus Access Read/Write Operation Parameter Symbol CS0 to CS7 setup t CSLCH CS0 to CS7 hold t CSHCH Address setup t ASCH Address hold t CHAX Valid address t AVDV valid data input time t CHWL WR0 ...
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CYC BA1 V OH MCLK, SYSCLK LBA CS0 CS7 A23 A00 RD D31 D16 WR0 WR1 D31 D16 ASLCH t ASHCH CSLCH ASCH V OH ...
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MB91307B (5) Ready Input Timing Parameter Symbol RDY setup time MCLK , t RDYS SYSCLK MCLK , SYSCLK t RDYH RDY hold time MCLK, SYSCLK t CHASL RDY Wait applied RDY Wait not applied 3.6 ...
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Hold Timing Parameter Symbol t CHBGL BGRNT delay time t CHBGH Pin floating t XHAL BGRNT time BGRNT valid time t HAHV Note: After a BRQ is accepted, a minimum of 1 cycle is required before BGRNT changes. t ...
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MB91307B (7) UART Timing Parameter Serial clock cycle time SCLK SOUT delay time Valid SIN SCLK SCLK valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCLK SOUT delay time Valid SIN SCLK SCLK valid ...
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Timer Clock Input Timing Parameter Symbol t TIWH Input pulse width t TIWL Note the cycle time of the peripheral system clock. CYCP TIN0 to TIN2 (9) Trigger Input Timing Parameter Symbol Pin name A/D startup trigger ...
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MB91307B (10) DMA Controller Timing Parameter Symbol DREQ input pulse width t DRWH DSTP input pulse width t DSWH t CLDL DACK delay time t CLDH t CLEL DEOP delay time t CLEH t CLIRL IORD delay time t CLIRH ...
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CYC BA1 V OH MCLK, SYSCLK DACK0 DACK2 DEOP0 DEOP2 t IORD t IOWR DREQ0 DREQ2 DSTP0 DSTP2 BA2 CLDL CLDH CLEL CLEH ...
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MB91307B 5. A/D Converter Electrical Characteristics ( Parameter Resolution Total error Linear error Differential linear error Zero transition error Full scale transition error Conversion time Analog port input current Analog input voltage Reference voltage Supply current Reference ...
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Definition of A/D Converter Terms • Resolution Indicates the ability of the A/D converter to discriminate analog variation • Linear error Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s zero transition point (00 0000 ...
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MB91307B • Total error Expresses the difference between actual and theoretical values as error, including zero transition error, full- scale error, and linearity error. 3FF 3FE 3FD 004 003 002 001 Total error in digital output N V ” (theoretical ...
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EXAMPLE CHARACTERISTICS (1) Sample output voltage characteristics (T Sample output H voltage (V ) characteristics OH 3.6 3.4 3.2 3.0 2.8 3.0 3.2 3.4 3.6 Supply voltage (V) (2) Sample input voltage characteristics (T Sample input H/L level characteristics (CMOS) ...
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MB91307B (Continued) Sample sleep current (I ) characteristics CCS ( MHz 3.0 3.2 3.4 3.6 Supply voltage (V) Sample A/D supply current (I ) characteristics MHz) A ...
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ORDERING INFORMATION Part number MB91307BPFV MB91V307RCR Package 120-pin, Plastic LQFP Lead-free package (FPT-120P-M21) 135-pin, Ceramic PGA For development tool use (PGA-135C-A02) MB91307B Remarks 85 ...
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MB91307B PACKAGE DIMENSION 120-pin, Plastic LQFP (FPT-120P-M21) 18.00±0.20(.709±.008)SQ 16.00±0.10(.630±.004) INDEX 120 LEAD No. 1 0.50(.020) 2001 FUJITSU LIMITED F120033S-c-3 0.08(.003) "A" +0.05 0.22±0.05 0.145 –0.03 0.08(.003) M (.009±.002) +.002 .006 –.001 Details ...
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MB91307B FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples ...