P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet
P60ARM-B
Related parts for P60ARM-B
P60ARM-B Summary of contents
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... Mitel Part Number: P60ARM-B/IG/GP1N Notes 1) The original P60ARM/CG/GPFR is obsolete 2) This datasheet includes the performance data previously supplied in supplement MS4396 - Jan 1996 ARM60 Data Sheet ...
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Preface The ARM60 is a low power, general purpose 32-bit RISC microprocessor implementation of the ARM6 macrocell, packaged in a 100 pin Metric Quad Flat Pack. Its simple, elegant and fully static design is particularly suitable for ...
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Introduction 1.1 ARM60 Block diagram 1.2 ARM60 Functional Diagram 2.0 Signal Description 3.0 Programmer's Model 3.1 Hardware Configuration 3.2 Operating Mode Selection 3.3 Registers 3.4 Exceptions 3.5 Reset 4.0 Instruction Set 4.1 Instruction Set Summary 4.2 The Condition Field ...
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... P60ARM-B 7.6 Load multiple registers 7.7 Store multiple registers 7.8 Data swap 7.9 Software interrupt and exception entry 7.10 Coprocessor data operation 7.11 Coprocessor data transfer (from memory to coprocessor) 7.12 Coprocessor data transfer (from coprocessor to memory) 7.13 Coprocessor register transfer (Load from coprocessor) 7.14 Coprocessor register transfer (Store to coprocessor) 7.15 Undefined instructions and coprocessor absent 7 ...
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Introduction The ARM60 is part of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer very low power consumption and price for high performance devices. The architecture is based on Reduced Instruction Set Computer (RISC) ...
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... P60ARM-B 1.1 ARM60 Block diagram A[31:0] ALE Address Register Register Bank (31 x 32bit registers status registers bit ALU Write Data Register DBE 2 ABE Address t Incrementer BoothÕs Multiplier Barrel ...
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ARM60 Functional Diagram MCLK Clocks nWAIT PROG32 DATA32 Configuration BIGEND LATEABT nIRQ Interrupts nFIQ nRESET ALE Bus DBE Controls ABE VDD Power VSS ARM60 Figure 2: ARM60 Functional Diagram Introduction TCK TMS Boundary TDI Scan nTRST TDO A[31:0] D[31:0] ...
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... P60ARM-B 4 ...
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Signal Description Name Type OS8 Addresses. This is the processor address bus. If ALE (address latch enable) is HIGH, the A[31:0] addresses become valid during phase 2 of the cycle before the one to which they refer and remain ...
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... P60ARM-B Name Type I Data bus enable. When DBE is LOW the write data register output drivers are disabled. DBE When DBE goes HIGH these output drivers are enabled. DBE facilitates data bus sharing for DMA and so on. LATEABT I Late abort. This signal controls the action of the processor on an abort exception. When it is HIGH (Late abort) the modified base register of an aborted LDR or STR instruction is written back ...
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Name Type nRESET I Not reset. This is a level sensitive input signal which is used to start the processor from a known address. A LOW level will cause the instruction being executed to terminate abnormally. When nRESET becomes HIGH ...
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... P60ARM-B Key to Signal Types Input IP - Input with pull-up resistor (35k - 100k ) O4 - Output (4mA drive) OS8 - slew-limited output (8mA drive Power 8 ...
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Programmer's Model ARM60 supports a variety of operating configurations. Some are controlled by inputs and are known as the hardware configurations . Others may be controlled by software and these are known as operating modes . 3.1 Hardware ConÞguration ...
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... P60ARM-B ARM60 supports six modes of operation: (1) User mode (usr): the normal program execution state (2) FIQ mode (fiq): designed to support a data transfer or channel process (3) IRQ mode (irq): used for general purpose interrupt handling (4) Supervisor mode (svc): a protected mode for the operating system ...
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General Registers and Program Counter User32 FIQ32 R8_fiq R9 R9_fiq R10 R10_fiq R11 R11_fiq R12 R12_fiq R13 R13_fiq R14 R14_fiq R15 (PC) R15 ...
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... P60ARM-B flags Figure 4: Format of the Program Status Registers (PSRs) The format of the Program Status Registers is shown in Figure 4: Format of the Program Status Registers (PSRs) . The and V bits are the condition code flags . The condition code flags in the CPSR may be changed as a result of arithmetic and logical operations in the processor and may be tested by all instructions to determine if the instruction executed ...
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Exceptions Exceptions arise whenever there is a need for the normal flow of program execution to be broken, so that (for example) the processor can be diverted to handle an interrupt from a peripheral. The processor state just prior ...
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... P60ARM-B To return normally from IRQ, use SUBS PC,R14_irq,#4 which will restore both the PC and the CPSR and resume execution of the interrupted code. R14_fiq is a symbol for the register R14 and if used needs to be declared in the users application program. 3.4.3 Abort An ABORT can be signalled by the external ABORT input. ABORT indicates that the current memory access cannot be completed ...
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The application program needs no knowledge of the amount of memory available to it, nor is its state in any ...
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... P60ARM-B 3.4.6 Vector Summary Address 0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010 0x00000014 0x00000018 0x0000001C These are byte addresses, and will normally contain a branch instruction pointing to the relevant routine. The FIQ routine might reside at 0x1C onwards, and thereby avoid the need for (and execution time of) a branch instruction ...
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Interrupt Latencies The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniser ( Tsyncmax ), plus the time for the longest instruction to complete ...
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... P60ARM-B 18 ...
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Instruction Set 4.1 Instruction Set Summary A summary of the ARM60 instruction set is shown in Figure 5: Instruction Set Summary . Note: some instruction codes are not defined but do not cause the Undefined instruction trap to be ...
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... P60ARM-B 4.2 The Condition Field Cond All ARM60 instructions are conditionally executed, which means that their execution may or may not take place depending on the values of the and V flags in the CPSR. The condition encoding is shown in Figure 6: Condition Codes . If the always (AL) condition is specified, the instruction will be executed irrespective of the flags. The never (NV) class of condition codes shall not be used as they will be redefined in future variants of the ARM architecture ...
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Branch and Branch with link (B, BL) The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 7: Branch Instructions . ...
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... P60ARM-B <expression> is the destination. The assembler calculates the offset. Items in {} are optional. Items in <> must be present. 4.3.4 Examples here BAL here B there CMP R1,#0 BEQ fred BL sub+ROM ADDS R1,#1 BLCC sub 22 ; assembles to 0xEAFFFFFE (note effect of PC offset) ; ALways condition used as default ; compare R1 with zero and branch to fred if R1 ...
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Data processing The instruction is only executed if the condition is true, defined at the beginning of this chapter. The instruction encoding is shown in Figure 8: Data Processing Instructions . The instruction produces a result by performing a ...
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... P60ARM-B 4.4.1 CPSR ßags The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected, the C ß ...
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Shifts When the second operand is specified shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left ...
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... P60ARM The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit the carry output. Logical shift right zero is redundant the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR # specified ...
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The form of the shift field which might be expected to give ROR #0 is used to encode a special function of the barrel shifter, rotate right extended (RRX). This is a rotate right by one bit position of ...
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... P60ARM-B (5) ASR more has result filled with and carry out equal to bit 31 of Rm. (6) ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm. (7) ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; ...
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Instruction Set - TEQ, TST, CMP & CMN Data Processing with PC written Data Processing with register secified shift and PC written S, I and N are as defined in section 5.1 Cycle types on page 65. 4.4.8 Assembler syntax ...
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... P60ARM-B 4.5 PSR Transfer (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set. The encoding is shown in Figure 15: PSR Transfer ...
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MRS (transfer PSR contents to a register Cond 00010 P s MSR (transfer register contents to PSR Cond 00010 d MSR (transfer register contents or immediate value ...
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... P60ARM-B 4.5.2 Reserved bits Only eleven bits of the PSR are defined in ARM60 (N,Z,C,V,I,F & M[4:0]); the remaining bits (= PSR[27:8,5]) are reserved for use in future versions of the processor. To ensure the maximum compatibility between ARM60 programs and future processors, the following rules should be observed: (1) The reserved bits shall be preserved when changing the value in a PSR. ...
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MSR - transfer immediate value to PSR flag bits only MSR{cond} <psrf>,<#expression> The expression should symbolise a 32 bit value of which the most significant four bits are written to the N,Z,C & V flags respectively. {cond} - two-character ...
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... P60ARM-B 4.6 Multiply and Multiply-Accumulate (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 16: Multiply Instructions. The multiply and multiply-accumulate instructions use a 2 bit Booth's algorithm to perform integer multiplication ...
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CPSR ßags Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of ...
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... P60ARM-B 4.7 Single data transfer (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 17: Single Data Transfer Instructions. The single data transfer instructions are used to load or store single bytes or words of data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register ...
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Offsets and auto-indexing The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted ...
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... P60ARM-B Big Endian Configuration A byte load (LDRB) expects the data on data bus inputs 31 through 24 if the supplied address word boundary, on data bus inputs 23 through word address plus one byte, and so on. The selected byte is placed in the bottom 8 bits of the destination register and the remaining bits of the register are filled with zeros ...
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Data Aborts A transfer to or from a legal address may cause problems for a memory management system. For instance system which uses virtual memory the required data may be absent from main memory. The memory manager ...
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... P60ARM-B [Rn,{+/-}Rm{,<shift>}]{!} offset of +/- contents of index register, shifted by <shift> (iii) A post-indexed addressing specification: [Rn],<#expression> offset of <expression> bytes [Rn],{+/-}Rm{,<shift>} offset of +/- contents of index register, shifted as by <shift>. Rn and Rm are expressions evaluating to a register number R15 then the assembler will subtract 8 from the offset value to allow for ARM60 pipelining. In this case base write-back shall not be specified. < ...
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Block data transfer (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 18: Block Data Transfer Instructions. Block ...
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... P60ARM-B the modified base is required (W=1). Figure 19: Post-increment addressing, Figure 20: Pre-increment addressing, Figure 21: Post-decrement addressing and Figure 22: Pre-decrement addressing show the sequence of register transfers, the addresses used, and the value of Rn after the instruction has completed. In all cases, had write back of the modified base not been required (W=0), Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction, when it would have been overwritten with the loaded value ...
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Rn 0x1000 0x0FF4 1 0x100C R5 R1 0x1000 0x0FF4 3 Figure 20: Pre-increment addressing 0x100C Rn 0x1000 0x0FF4 1 0x100C 0x1000 R5 R1 0x0FF4 3 Figure 21: Post-decrement addressing Instruction Set - LDM, STM ...
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... P60ARM 4.8.4 Use of the S bit When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged mode. LDM with R15 in transfer list and S bit set (Mode changes) If the instruction is a LDM then SPSR_< ...
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Use of R15 as the base R15 shall not be used as the base register in any LDM or STM instruction. 4.8.6 Inclusion of the base in the register list When write-back is specified, the base is written back ...
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... P60ARM-B STM instructions take (n-1 incremental cycles to execute the number of words transferred. 4.8.9 Assembler syntax <LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^} {cond} - two character condition mnemonic, see Figure 6: Condition Codes expression evaluating to a valid register number <Rlist> list of registers and register ranges enclosed in {} (eg {R0,R2-R7,R10}). ...
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IA, IB, DA, DB allow control when LDM/STM are not being used for stacks and simply mean Increment After, Increment Before, Decrement After, Decrement Before. 4.8.10 Examples LDMFD SP!,{R0,R1,R2} STMIA R0,{R0-R15} LDMFD SP!,{R15} LDMFD SP!,{R15}^ STMFD R13,{R0-R14}^ These instructions may ...
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... P60ARM-B 4.9 Single data swap (SWP) The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 23: Swap Instruction. The data swap instruction is used to swap a byte or word quantity between a register and external memory. ...
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Data Aborts If the address used for the swap is unacceptable to a memory management system, the internal MMU or external memory manager can flag the problem by driving ABORT HIGH. This can happen on either the read or ...
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... P60ARM-B 4.10 Software interrupt (SWI) The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 24: Software Interrupt Instruction. The software interrupt instruction is used to enter Supervisor mode in a controlled manner. The instruction causes the software interrupt trap to be taken, which effects the mode change ...
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Examples SWI ReadC SWI WriteI+”k” SWINE 0 The above examples assume that suitable supervisor code exists, for instance: 0x08 B Supervisor EntryTable DCD ZeroRtn DCD ReadCRtn DCD WriteIRtn . . . Zero EQU 0 ReadC EQU 256 WriteI EQU ...
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... P60ARM-B 4.11 Coprocessor data operations (CDP) The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 25: Coprocessor Data Operation Instruction. This class of instruction is used to tell a coprocessor to perform some internal operation. No result is communicated back to ARM60, and it will not wait for the operation to complete ...
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Assembler syntax CDP{cond} p#,<expression1>,cd,cn,cm{,<expression2>} {cond} - two character condition mnemonic, see Figure 6: Condition Codes p# - the unique number of the required coprocessor <expression1> - evaluated to a constant and placed in the CP Opc field cd, cn ...
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... P60ARM-B 4.12 Coprocessor data transfers (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 26: Coprocessor Data Transfer Instructions. This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessorsÕs registers directly to memory ...
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Addressing modes ARM60 is responsible for providing the address used by the memory system for the transfer, and the addressing modes available are a subset of those used in single data transfer instructions. Note, however, that the immediate offsets ...
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... P60ARM-B LDC - load from memory to coprocessor STC - store from coprocessor to memory {L} - when present perform long transfer (N=1), otherwise perform short transfer (N=0) {cond} - two character condition mnemonic, see Figure 6: Condition Codes p# - the unique number of the required coprocessor expression evaluating to a valid coprocessor register number that is placed in the CRd field < ...
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Coprocessor register transfers (MRC, MCR) The is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction encoding is shown in Figure 27: Coprocessor Register Transfer Instructions. This class ...
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... P60ARM-B specify the operation the coprocessor is required to perform, CRn is the coprocessor register which is the source or destination of the transferred information, and CRm is a second coprocessor register which may be involved in some way which depends on the particular operation specified. 4.13.2 Transfers to R15 When a coprocessor register transfer to ARM60 has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the and V flags respectively ...
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MRCEQ 3,9,R3,c5,c6,2 Instruction Set - MRC, MCR ; conditionally request coproc 3 to perform ; operation 9 (type and c6, and ; transfer the result back ...
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... P60ARM-B 4.14 UndeÞned instruction The instruction is only executed if the condition is true. The various conditions are defined at the beginning of this chapter. The instruction format is shown in Figure 28: Undefined Instruction. If the condition is true, the undefined instruction trap will be taken Cond 011 Note that the undefined instruction mechanism involves offering this instruction to any coprocessors which may be present, and all coprocessors must refuse to accept it by driving CPA and CPB HIGH ...
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Instruction Set Examples The following examples show ways in which the basic ARM60 instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just ...
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... P60ARM-B BCC Div1 MOV Rc,#0 Div2 CMP Ra,Rb SUBCS Ra,Ra,Rb ADDCS Rc,Rc,Rcnt MOVS Rcnt,Rcnt,LSR#1 MOVNE Rb,Rb,LSR#1 BNE Div2 4.15.2 Pseudo random binary sequence generator It is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift generators with exclusive-OR feedback rather like a cyclic redundancy check generator. Unfortunately the sequence bit generator needs more than one feedback tap to be maximal length (i ...
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Multiplication by 6 ADD Ra,Ra,Ra,LSL #1 MOV Ra,Ra,LSL#1 (5) Multiply by 10 and add in extra number ADD Ra,Ra,Ra,LSL#2 ADD Ra,Rc,Ra,LSL#1 (6) General recursive method for Rb := Ra* constant: ( even, say C = ...
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... P60ARM-B 4.15.4 Loading a word from an unknown alignment BIC Rb,Ra,#3 LDMIA Rb,{Rd,Rc} AND Rb,Ra,#3 MOVS Rb,Rb,LSL#3 MOVNE Rd,Rd,LSR Rb RSBNE Rb,Rb,#32 ORRNE Rd,Rd,Rc,LSL Rb 4.15.5 Loading a halfword (Little Endian) LDR Ra, [Rb,#2] MOV Ra,Ra,LSL #16 MOV Ra,Ra,LSR #16 4.15.6 Loading a halfword (Big Endian) LDR Ra, [Rb,#2] MOV Ra,Ra,LSR # enter with address in Ra (32 bits) ; uses Rb, Rc; result in Rd. ...
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Memory Interface ARM60 communicates with its memory system via a bidirectional data bus ( D[31: separate 32 bit address bus specifies the memory location to be used for the transfer, and the nRW signal gives the direction ...
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... P60ARM-B MCLK A[31:0] nMREQ SEQ nRAS nCAS D[31:0] When an S-cycle follows an N-cycle, the address will always be one word greater than the address used in the N-cycle. This address (marked ÒaÓ in the above diagram) should be checked to ensure that it is not the last in the DRAM page before the memory system commits to the S-cycle the page end, the S-cycle cannot be performed in page mode and the memory system will have to perform a full access ...
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MCLK A[31:0] nMREQ SEQ nRAS nCAS D[31: byte write is requested (STRB), ARM60 will broadcast the byte value across the data bus, presenting it at each byte location within the word. The memory system must decode A[1:0] to ...
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... P60ARM-B A[0] A[1] Figure 31: Decoding Byte Accesses to Memory 5.3 Address timing Normally the processor address changes during phase 2 to the value which the memory system should use during the following cycle. This gives maximum time for driving the address to large memory arrays, and for address translation where required. Dynamic memories usually latch the address on chip, and if the latch is timed correctly they will work even though the address changes before the access has completed ...
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Address translation will normally only be necessary on an N-cycle, and this fact may be exploited to reduce power consumption in the memory manager and avoid the translation delay at other times. The times when translation is necessary can be ...
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... P60ARM-B 70 ...
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Coprocessor Interface The functionality of the ARM60 instruction set may be extended by the addition external coprocessors. When the coprocessor is not present, instructions intended for it will trap, and suitable software may be installed ...
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... P60ARM-B 6.2 Data transfer cycles Once the coprocessor has gone not-busy in a data transfer instruction, it must supply or accept data at the ARM60 bus rate (defined by MCLK and nWAIT ). It can deduce the direction of transfer by inspection of the L bit in the instruction, but must only drive the bus when permitted to by DBE being HIGH. The coprocessor is responsible for determining the number of words to be transferred ...
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The coprocessor must therefore preserve the original floating point value and not corrupt it during the conversion, because it will be required again if an interrupt arises during the busy period. The coprocessor data operation class ...
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... P60ARM-B 74 ...
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Instruction Cycle Operations In the following tables nMREQ and SEQ (which are pipelined up to one cycle ahead of the cycle to which they apply) are shown in the cycle in which they appear, so they predict the type ...
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... P60ARM-B An instruction prefetch occurs at the same time as the above operation, and the program counter is incremented. When the shift length is specified by a register, an additional datapath cycle occurs before the above operation to copy the bottom 8 bits of that register into a holding latch in the barrel shifter. The instruction prefetch will occur during this first cycle, and the operation cycle will be internal (ie will not request memory) ...
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Multiply and multiply accumulate The multiply instructions make use of special hardware which implements a 2 bit Booth's algorithm with early termination. During the first cycle the accumulate Register is brought to the ALU, which either transmits it or ...
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... P60ARM-B 7.4 Load register The first cycle of a load register instruction performs the address calculation. The data is fetched from memory during the second cycle, and the base register modification is performed during this cycle (if required). During the third cycle the data is transferred to the destination register, and external memory is unused ...
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Store register The first cycle of a store register is similar to the first cycle of load register. During the second cycle the base modification is performed, and at the same time the data is written to memory. There ...
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... P60ARM-B Cycle 1 register register 1 dest= registers 1 (n>1) 2 • n n+1 n+2 n registers 1 (n>10) 2 incl pc • n n+1 n+2 n+3 n+4 Table 12: Load Multiple Registers Instruction Cycle Operations 80 Address nBW nRW pc alu 1 0 pc+ pc+12 pc alu 1 0 pc+ pc’ pc’+ pc’+8 ...
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Store multiple registers Store multiple proceeds very much as load multiple, without the final cycle. The restart problem is much more straightforward here, as there is no wholesale overwriting of registers to contend with. The cycle timings are shown ...
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... P60ARM-B Cycle Address 1 pc pc+12 pc+12 Table 14: Data Swap Instruction Cycle Operations 7.9 Software interrupt and exception entry Exceptions (and software interrupts) force the particular value and refill the instruction pipeline from there. During the first cycle the forced address is constructed, and a mode change may take place. The return address is moved to R14 and the CPSR to SPSR_svc ...
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Coprocessor data operation A coprocessor data operation is a request from ARM60 for the coprocessor to initiate some action. The action need not be completed for some time, but the coprocessor must commit to doing it before driving CPB ...
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... P60ARM-B Cycle Address 1 register 1 pc+8 ready 2 alu pc+12 1 register 1 pc+8 not ready 2 pc+8 • pc+8 n pc+8 n+1 alu pc+12 n registers 1 pc+8 (n>1) 2 alu ready • alu+• n alu+• n+1 alu+• pc+12 m registers 1 pc+8 (m>1) 2 pc+8 not ready • pc+8 n pc+8 n+1 alu • alu+• n+m alu+• n+m+1 alu+• pc+12 Table 17: Coprocessor Data Transfer Instruction Cycle Operations ...
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Coprocessor data transfer (from coprocessor to memory) The ARM60 controls these instructions exactly as for memory to coprocessor transfers, with the one exception that the nRW line is inverted during the transfer cycle. The cycle timings are show in ...
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... P60ARM-B 7.13 Coprocessor register transfer (Load from coprocessor) Here the busy-wait cycles are much as above, but the transfer is limited to one data word, and ARM60 puts the word into the destination register in the third cycle. The third cycle may be merged with the following prefetch cycle into one memory N-cycle as with all ARM60 register load instructions ...
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Cycle Address ready 1 pc+8 2 pc+12 pc+12 not ready 1 pc+8 2 pc+8 • pc+8 n pc+8 n+1 pc+12 pc+12 Table 20: Coprocessor register transfer (Store to coprocessor) 7.15 UndeÞned instructions and coprocessor absent When a coprocessor detects a ...
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... P60ARM-B Cycle Address 1 pc+8 pc+12 Table 22: Unexecuted Instruction Cycle Operations 7.17 Instruction Speed Summary Due to the pipelined architecture of the CPU, instructions overlap considerably typical cycle one instruction may be using the data path while the next is being decoded and the one after that is being fetched ...
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Boundary Scan Test Interface The boundary-scan interface conforms to the IEEE Std. 1149.1- 1990, Standard Test Access Port and Boundary-Scan Architecture (please refer to this standard for an explanation of the terms used in this section and for a ...
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... P60ARM-B 8.2 Reset The boundary-scan interface includes a state-machine controller (the TAP controller). In order to force the TAP controller into the correct state after power-up of the device, a reset pulse must be applied to the nTRST pin. If the boundary scan interface used, then nTRST must be driven LOW, and then HIGH again ...
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The EXTEST instruction connects the BS register between TDI and TDO . When the instruction register is loaded with the EXTEST instruction, all the boundary-scan cells are placed in their test mode of operation. In the CAPTURE-DR state, inputs from ...
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... P60ARM-B When the HIGHZ instruction is loaded into the instruction register, all outputs are placed in an inactive drive state. In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is shifted into the bypass register via TDI and out via TDO after a delay of one TCK cycle. Note that the first bit shifted out will be a zero ...
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... ID register. In the SHIFT-DR state, the previously captured device identification code is shifted out of the ID register via the TDO pin, whilst data is shifted in via the TDI pin into the ID register. In the UPDATE-DR state, the ID register is unaffected. The device identification codes for the P60ARM (obsolete) and P60ARM-B are as follows: P60ARM 1 ...
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... P60ARM-B 8.6 Test Data Registers Figure 33: Boundary Scan Block Diagram illustrates the structure of the boundary scan logic. BSINENCELL BSINCELL BSOUTNENCELL TDI TMS TCK nTRST 8.6.1 Bypass Register Purpose: This is a single bit register which can be selected as the path between TDI and TDO to allow the device to be bypassed during boundary-scan testing ...
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There is no parallel output from the bypass register. A logic 0 is loaded from the parallel input of the bypass register in the CAPTURE-DR state. 8.6.2 ARM60 Device IdentiÞcation (ID) Code Register Purpose: This register is used to read ...
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... P60ARM-B The correspondence between boundary-scan cells and system pins, system direction controls and system output enables is as shown in Table 25: Boundary Scan Signals & Pins . The cells are listed in the order in which they are connected in the boundary-scan register, starting with the cell closest to TDI . All boundary- scan register cells at input pins can apply tests to the on-chip core logic. The EXTEST guard values specified in Table 25: Boundary Scan Signals & ...
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Boundary Scan Interface Signals TCK TMS TDI TDO T bsoh Data In Data Out T bsdh TCK TDO T bsoe Data Out T bsde nTRST TMS Boundary Scan Test Interface T bscl T T bsis T bsod T T ...
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... P60ARM-B Symbol TCK low period Tbscl Tbsch TCK high period Tbsis TDI,TMS setup to [TCr] TDI,TMS hold from [TCr] Tbsih TCf to TDO valid Tbsod Tbsoh TDO hold time Tbsoe TDO enable time TDO disable time Tbsoz Tbsss I/O signal setup to [TCr] Tbssh I/O signal hold from [TCr] ...
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No. Cell Name Pin Type from tdi 1 din0 D[ dout0 D[0] OUT 3 din1 D[ dout1 D[1] OUT 5 din2 D[ dout2 D[2] OUT 7 din3 D[ dout3 D[3] OUT 9 ...
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... P60ARM-B No. Cell Name Pin Type 98 a22 A[22] OUT 99 a21 A[21] OUT 100 a20 A[20] OUT 101 a19 A[19] OUT 102 a18 A[18] OUT 103 a17 A[17] OUT 104 a16 A[16] OUT 105 a15 A[15] OUT 106 a14 A[14] OUT 107 a13 A[13] OUT 108 a12 A[12] OUT 109 a11 A[11] OUT 110 a10 ...
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DC Parameters 9.1 Absolute Maximum Ratings Symbol Parameter VDD Supply voltage Vip Voltage applied to input pin Vop Voltage applied to output pin Osct Output short circuit time Ts Storage temperature Ta Ambient operating temperature Pd Maximum power dissipation ...
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... P60ARM-B 9.2 DC Operating Conditions Symbol Parameter VDD Supply voltage Vih Input HIGH voltage Vil Input LOW voltage Io4 Output current (O4 outputs) Io8 Output current (OS8 outputs) Ta Ambient operating temperature Notes: Voltages measured with respect to VSS. (1) Theses levels apply to all inputs of type I and IP. Particular care needs to be taken with clock inputs in the PCB layout to eliminate EMC noise and provide true supply voltages directly at the device pins ...
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For Vin = 0 to VDD and only for inputs without pullup resistors. (4) When sourcing or sinking the maximum rated output current for the output driver ( 4 or 8mA). (5) Only certain inputs have pullup resistors. DC ...
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... P60ARM-B 104 ...
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AC Parameters The AC timing diagrams presented in this section assume that the outputs of the ARM60 have been loaded with the capacitive loads shown in the `Test Load' column of Table 29: AC Test Loads . These loads ...
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... P60ARM-B MCLK A[31:0] nRW nBW, LOCK nTRANS nOPC nMREQ, SEQ Note: nWAIT , ABE and ALE are all HIGH during the cycle shown. MCLK ALE A[31:0] Note: Tald is the time by which ALE must be driven LOW in order to latch the current address in phase 2. If ALE is driven low after Tald, then a new address may be latched. ABE is high during the cycle shown ...
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MCLK ABE A[31:0] Note: Tabz is the tristate turn off time, Tabe is the address enable time (turn on), relative to ABE . ALE is high during the cycle shown. MCLK D[31:0] Note: DBE is high during the cycle shown. ...
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... P60ARM-B MCLK D[31: DBE Note: The cycle shown is a data write cycle. Here, DBE has been used to modify the behaviour of the data bus. MCLK LATEABT, BIGEND, DATA32, PROG32 MCLK nCPI CPA, CPB nMREQ, SEQ Note: Normally, nMREQ and SEQ become valid Tmsd after the falling edge of MCLK . In this cycle the ARM has been busy-waiting, waiting for a coprocessor to complete the instruction ...
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MCLK ABORT nRESET nFIQ, nIRQ Note: Tirs, Trs guarantee recognition of the interrupt (or reset) source by the corresponding clock edge. Tirm, Trh guarantee non-recognition by that clock edge. These inputs may be applied fully asynchronously where the exact cycle ...
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... P60ARM* Parameter Min Table 30: AC Parameters (units of nS) P60ARM-B Max Min Max ...
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... Table 30 also includes data fpr the obsolete P60ARM for convenience. Customers replacing the P60ARM by the P60ARM-B should check that timing differences betweem the two devices will not cause operational problems. Note in particular that Tah and Tde are marginally less for the -B version ...
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... P60ARM-B 10.1 Notes on AC Parameters 1. Tristate output times: 2. For a valid RESET, NRESET must remain low for a minimum of two MCLK cycles. 112 ...
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Physical Details Pin 1 Pin 30 Figure 47: ARM60 100 Pin Metric Plastic QFP Mechanical Dimensions in mm 17.90 0.25 14.00 0.10 Pin 100 Pin 81 ARM60 Pin 31 0.65 typ 0.30 Physical Details Pin 80 Pin 51 Pin ...
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... P60ARM-B 114 ...
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Pinout Pin Signal 1 D[27] 2 D[28] 3 D[29] 4 D[30] 5 D[31] 6 CPA 7 Vss 8 Vdd 9 LOCK 10 BIGEND 11 nCPI 12 DBE 13 nBW 14 MCLK 15 nWAIT 16 LATEABT 17 PROG32 18 DATA32 ...
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North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 3213 South America Tel/Fax: +55 (48) 225 2061 Information relating to products and circuits (“Product”) furnished herein by Mitel Corporation or its subsidaries (“Mitel”) is believed to be reliable. ...
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... South America Tel/Fax: +55 (48) 225 2061 Preliminary and Advance Data/Information: Some datasheets carry the designation “Preliminary” or “Advance”. Preliminary Information represents the design objective for a device type in development and may be revised without notice before the device reaches production. Advance Information is intended for design guidance purposes and refers to a device type in early production where device characterization is ongoing and information is still subject to change without notice ...