ADP3804 Analog Devices, ADP3804 Datasheet - Page 6

• Manufacturer Part Number: ADP3804
• Description: High Frequency Switch Mode Li-Ion Battery Charger
• Manufacturer: Analog Devices

ADP3804
Typical values of R
and the input range of ISET is from 0 V to 4 V. If, for example,
a 2 A charger is required, then R
V
below 500 mW. In this example, the power is a maximum of
200 mW. Once R
adjusted during operation with V
125 mV gives a charge current of 100 mA for trickle charging.
Components R3, R4, and C13 provide high frequency filtering
for the current sense signal.
Final Battery Voltage Control
As the battery approaches its final voltage, the ADP3804
switches from CC mode to CV mode. The change is achieved
by the common output node of g
two outputs controls the voltage at the COMP pin. Both ampli-
fiers can only pull down on COMP, such that when either
amplifier has a positive differential input voltage, its output is
not active. For example, when the battery voltage, V
g
the desired final voltage, g
charge current is reduced.
Amplifier g
ence voltage of 2.5 V. In the case of the ADP3804-12.5 and
ADP3804-12.6, an internal resistor divider sets the final battery
voltage to 12.6 V. In contrast, the ADP3804 requires external,
precision resistors. The divider ratio should be set to divide the
desired final voltage down to 2.5 V at the BAT pin:
These resistors should be high impedance to limit the battery
leakage current. Alternatively, an external NMOS can be added
in series with R12 to turn off during shutdown. In the case of
the ADP3804-12.5 and ADP3804-12.6, an internal MOSFET
disconnects the internal divider to reduce the leakage current
into BAT to less than 1 µA during shutdown. If the ADP3804-
12.5 or ADP3804-12.6 is used, then R11 should be shorted
and R12 open. The reference and internal resistor divider are
referenced to the AGND pin, which should be connected close
to the negative terminal of the battery to minimize sensing
errors.
Final Battery Voltage Adjust
The ADJ pin provides an analog input to adjust the final bat-
tery voltage by ± 5%. Figure 2 shows the control curve for this
amplifier. Above the threshold voltage of 4.6 V, the amplifier is
turned off. Thus, to disable this function, ADJ should be con-
nected to REG. In the linear range between 1 V and 4 V, the
percentage change in V
This percent change is the same for the ADP3804 (2.5 V out-
put) and the ADP3804-12.6.
Oscillator and PWM
The oscillator generates a triangle waveform between 1 V and
2.5 V, which is compared to the voltage at the COMP pin,
setting the duty cycle of the driver stage. When V
1 V, the duty cycle is zero. Above 2.5 V, the duty cycle reaches
its maximum. The ADP3804 forces a minimum off time of
m2
ISET
does not control V
R
R
= 2.5 V. The power dissipation in R
V
11
12
BAT
m2
V
BATTERY
%
compares the battery voltage to the internal refer-
2.5
V
CS
100
CS
has been chosen, the charge current can be
are in the range from 25 m to 50 m ,
COMP
BAT
V
1
ADJ
m2
is a function V
. When the battery voltage reaches
30
takes control of the loop, and the
2.5
CS
m1
ISET
V
could be set to 50 m and
and g
. Lowering V
m2
ADJ
CS
. Only one of the
should be kept
as follows:
COMP
ISET
BAT
to
(2)
(3)
is below
, is low,
–6–
approximately 200 nsec to ensure that the boost capacitor is
always charged. This off time sets the maximum duty cycle.
For example, a 200 kHz frequency (5 µsec period) gives a
maximum duty cycle of 96%.
The oscillator frequency is set by the external capacitor at the
CT pin and the internal current source of 150 µA according to
the following formula:
A 200 pF capacitor sets the frequency to 250 kHz. The fre-
quency can also be synchronized to an external oscillator by
applying a square wave input on SYNC. The SYNC function is
designed to allow only increases in the oscillator frequency.
The f
duty cycle of the SYNC input is not important and can be
anywhere between 5% and 95%.
7V Boost Regulator
The driver stage is powered by the internal 7V boost regulator,
which is available at the BSTREG pin. Because the switching
currents are supplied by this regulator, decoupling must be
added. A 0.1 µF capacitor should be placed close to the
ADP3804, with the ground side connected close to the power
ground pin, PGND. This supply is not recommended for use
externally due to high switching noise.
Boosted Synchronous Driver
The PWM comparator controls the state of the synchronous
driver. A high output from the PWM comparator forces DRVH
on and DRVL off. The drivers have an ON resistance of ap-
proximately 5
nal MOSFETs. Furthermore, the boosted drive allows an
external NMOS transistor for the main switch instead of a
PMOS. A boost diode is internally connected between
BSTREG and BST, and a boost capacitor of 0.1 µF must be
added externally between BST and SW. The voltage between
BST and SW is typically 6 V.
The DRVL pin switches between BSTREG and PGND. The 7
V output of BSTREG drives the external NMOS with high
VGS to lower the ON resistance. PGND should be connected
close to the source pin of the external synchronous NMOS.
When DRVL is high, this turns on the lower NMOS and pulls
the SW node to ground. At this point, the boost capacitor is
charged up through the internal boost diode. When the PWM
switches high, DRVL is turned off and DRVH turns on.
DRVH switches between BST and SW. When DRVH is on,
the SW pin is pulled up to the input supply (typically 16 V),
and BST rises above this voltage by approximately 6 V.
Overlap protection is included in the driver to ensure that both
external MOSFETs are not on at the same time. When DRVH
turns off the upper MOSFET, the SW node goes low due to
the inductor current. The ADP3804 monitors the SW voltage,
and turns on DRVL when SW goes below 1 V. If, under low
current loads, the SW voltage does not drop below 1 V, DRVL
will turn on after time-out of 200 nsec. When DRVL turns off,
an internal timer adds a delay of 50 nsec before turning DRVH
on.
f
OSC
SYNC
2
should be no more than 20% higher than f
CT
150
for fast rise and fall times when driving exter-
1.5
A
V
OSC
(4)
REV. PrI
. The