L64105 LSI Logic Corporation, L64105 Datasheet - Page 307
L64105
Manufacturer Part Number
L64105
Description
Mpeg-2 Audio/video Decoder
Manufacturer
LSI Logic Corporation
Datasheet
1.L64105.pdf
(454 pages)
- Current page: 307 of 454
- Download datasheet (5Mb)
Next, the host must set the Display Override Luma and Chroma Frame
Store Start Addresses. These are the DMA SDRAM Target addresses
the host used for the two stores or the Luma and Chroma Base
Addresses for a decoded picture.
In addition to the address pointers, the host must also program the width
of the image using the Override Picture Width field. The picture
width register has a resolution of 8 pixels, hence the frame store image
width must be in 8-pixel increments. This picture width register is used
by the Display Controller for accessing subsequent lines of the frame
store.
To display a still picture it stored, the host adjusts the main display area
if necessary, sets or clears the Host Top Field First bit as desired, enters
the Decode Stop Command, and sets the Display Override Mode. The
Video Decoder may be left running during the still display.
Display override has two modes, field and frame. Field Mode is provided
for field structure pictures where motion between the fields may cause
distortion of the image. In Field Mode, the first field is controlled by the
Host Top Field First bit and is output during both field times. In Frame
Mode, both fields are output to the display.
When enabled, the still image is processed through the horizontal and
vertical filters of the Video Decoder. The override picture width and the
main reads per line are separate registers and allows the flexibility of
displaying a portion of the still image frame store (necessary for pan and
scan scaling of a still frame).
When the Display Controller is programmed for still image display, the
data is simply read from the Display Override Frame Stores instead of
the frame store indicated by the video decode engine. The parameters
for the Display Override Frame Stores are sampled internally at every
field boundary, allowing the host to change the values in the middle of
the field.
It is possible to display a still image and continue to decode video in the
background. As long as the decoder is started and freeze is not active,
the Display Controller continues to issue decode signals to the decoder.
When a freeze is issued, the Display Controller temporarily suspends
decoding while the freeze is active. This property can be exploited for
various trick modes that require random access.
Still Image Display
9-15
Related parts for L64105
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Satellite Decoder Technical Manual 5/97
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Satellite Receiver
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Tuner/receiver Chipset
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Tuner And Satellite Receiver Chipset Data Sheet 2/01
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Smatv Qam Encoder
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
DVB Qam Modulator
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Dvb-t Cofdm Demodulator Technical Manual 2/00
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
16-Bit HCMOS Multiplier / Accumulators
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
Transport with Embedded CPU and Control
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
32-Bit HCMOS IEEE Floating-Point Processor
Manufacturer:
LSI Logic Corporation
Part Number:
Description:
Controllers, Transport Controller with Embedded MIPS CPU (TR4101)
Manufacturer:
LSI Logic Corporation
Datasheet:
Part Number:
Description:
Variable-Length Video Shift Registers
Manufacturer:
LSI Logic Corporation