MD16R1624DF0 Samsung Semiconductor, Inc., MD16R1624DF0 Datasheet - Page 6

• Manufacturer Part Number: MD16R1624DF0
• Description: Description = MD16R1624(8/G)DF0, MD18R1624(8/G)DF0 (16Mx16)*4(8/16)pcs RIMM(TM) Module Based on 256Mb D-die, 32s Banks,16K/32ms Ref, 2.5V ;; Density(MB) = 128 ;; Organization = 32Mx32 ;; Component Composition = 256M(5th)x4 ;; Voltage(V) = 2.5 ;; Refr
• Manufacturer: Samsung Semiconductor, Inc.

MD16R1624(8/G)DF0 - CN1 for 1200MHz
MD18R1624(8/G)DF0 - CN1 for 1200MHz
SOUT_THRU
CFM_TERM
CFMN_TERM
CMD_TERM
COL4_TERM..
COL0_TERM
CTM_TERM_L
CTM_TERM_R
CTMN_TERM_L
CTMN_TERM_R
DQA8_TERM..
DQA0_TERM
DQB8_TERM..
DQB0_TERM
ROW2_TERM..
ROW0_TERM
SCK_TERM
Signal
A34
B103
B101
A115
B97, A97, B95, A95, B93
B73
A103
B71
A105
B113, A113, B111, A111,
B109, A109, B107, A107,
B105
A85, B85, A87, B87, A89,
B89, A91, B91, A93
A101, B99, A99
B115
Module Connector Pads
Table 3: Module Connector Pad Description (Continued)
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
V
V
V
Type
RSL
RSL
RSL
RSL
RSL
RSL
RSL
RSL
RSL
RSL
CMOS
CMOS
CMOS
Page 5
"Thru" Channel Serial I/O for reading from and writing to the con-
trol registers. Attaches to SIO1 of left RDRAM device on "Thru"
Channel.
Clock from master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for receiving RSL signals from the
controller. Positive polarity.
Clock from master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for receiving RSL signals from the
controller. Negative polarity.
Serial Command Input used to read from and write to the control
registers. Also used for power management. Connects to right
RDRAM device on "Term" Channel.
"Term" Channel Column bus. 5-bit bus containing control and
address information for column accesses. Connects to right
RDRAM device on "Term" Channel.
Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to the
controller. Positive polarity.
Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to the
controller. Positive polarity.
Clock To Master. Connects to left RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
Clock To Master. Connects to right RDRAM device on "Term"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
"Term" Channel Data bus A. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Term”
Channel. Connects to right RDRAM device on "Term" Channel.
DQA8_TERM is non-functional on modules with x16 RDRAM
devices.
"Term" Channel Data bus B. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Term”
Channel. Connects to right RDRAM device on "Term" Channel.
DQB8_TERM is non-functional on modules with x16 RDRAM
devices.
"Term" Channel Row bus. 3-bit bus containing control and address
information for row accesses. Connects to right RDRAM device on
"Term" Channel.
Serial Clock input. Clock source used to read from and write to
"Term" Channel RDRAM control registers. Connects to right
RDRAM device on "Term" Channel.
Version 1.0 January 2003
32 Bit RIMM
Description
®
Module