AD9849 Analog Devices, AD9849 Datasheet - Page 12

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AD9849

Manufacturer Part Number
AD9849
Description
CCD Signal Processors with Integrated Timing Driver
Manufacturer
Analog Devices
Datasheet

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AD9848/AD9849
SERIAL INTERFACE TIMING
COMPLETE REGISTER LISTING
Register
oprmode
ctlmode
preventpdate
readback
vdhdpol
fieldval
hblkretime
tgcore_rstb
h12pol
h1posloc
h1negloc
Notes on Register Listing:
1. All addresses and default values are expressed in Hexadecimal.
2. All registers are VD/HD updated as shown in Figure 3, except for the above-listed registers that are SL updated.
SDATA
SCK
SL
SDATA
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 6-BIT DATA WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA WORD (ALL 6 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE, OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
SCK
Description
AFE Operation Modes
AFE Control Modes
Prevents Loading of VD-Updated Registers
Enables Serial Register Readback Mode
VD/HD Active Polarity
Internal Field Pulse Value
Retimes the H1 hblk to Internal Clock
Reset Bar Signal for Internal TG Core
H1/H2 Polarity Control
H1 Positive Edge Location
H1 Negative Edge Location
SL
VD
HD
A0
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS.
3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED.
4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE, OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
A1
A0
t
A2
DS
t
A1
LS
A3
A2
A4
A3
A5
t
A4
DH
A6
A5
A7
A6
D0
A7
DATA FOR STARTING
REGISTER ADDRESS
D1
D0
D2
Table I
D1
h3drv
D3
Register
h1drv
h2drv
h4drv
rgpol
rgposloc
rgnegloc
rgdrv
shpposloc
shdposloc
D2
D4
D3
D5
t
D4
LH
D0
D5
H1 Drive Current
H3 Drive Current
H4 Drive Current
RG Positive Edge Location
SHP Sample Location
Description
H2 Drive Current
RG Polarity
RG Negative Edge Location
RG Drive Current
SHD Sample Location
D1
REGISTER ADDRESS
SL UPDATED
XX
DATA FOR NEXT
D2
XX
D3
D4
D5
VD/HD UPDATED
D0
D1
D2
...
...
...

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