AD9985 Analog Devices, AD9985 Datasheet - Page 16

• Manufacturer Part Number: AD9985
• Description: 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
• Manufacturer: Analog Devices

AD9985
disappear. In other systems, such as those that employ
Composite Sync (Csync) signals or embedded Sync-on-Green
(SOG), Hsync includes equalization pulses or other distortions
during Vsync. To avoid upsetting the clock generator during
Vsync, it is important to ignore these distortions. If the pixel
clock PLL sees extraneous pulses, it will attempt to lock to this
new frequency, and will have changed frequency by the end of
2-WIRE SERIAL REGISTER MAP
The AD9985 is initialized and controlled by a set of registers, that determine the operating modes. An external controller is employed to
write and read the control registers through the two-line serial interface port.
Table 10. Control Register Map
Hex
Address
00H
01H*
02H*
Write and
Read or
Read Only
RO
R/W
R/W
DATACK
.
DATACK
ADCCK
HSYNC
HSOUT
ADCCK
HSYNC
HSOUT
RGB
G
R
RGB
D
PxCK
PxCK
OUTA
OUTA
OUTA
HS
HS
IN
IN
Bits
7:0
7:0
7:4
P0
P0
Default
Value
01101001
1101****
P1
P1
5-PIPE DELAY
5-PIPE DELAY
P2
P2
P3
P3
Chip Revision
Register Name
PLL Div MSB
PLL Div LSB
P4
P4
Figure 10. 4:4:4 Mode (For RGB and YUV)
Figure 11. 4:2:2 Mode (For YUV Only)
P5
P5
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U0
Y0
D0
P6
P6
Y1
V1
D1
P7
P7
An 8-bit register that represents the silicon revision level.
This register is for Bits [11:4] of the PLL divider. Greater values mean
Function
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. This will give the PLL more time to lock.
Bits [7:4] of this word are written to the LSBs [3:0] of the PLL divider
word.
Y2
U2
D2
VARIABLE DURATION
VARIABLE DURATION
the Vsync period. It will then take a few lines of correct Hsync
timing to recover at the beginning of a new frame, resulting in a
“tearing” of the image at the top of the display.
The COAST input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and allows the
clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
Y3
V3
D3
U4
D4
Y4
D5
Y5
V5
U6
D6
Y6
D7
Y7
V7