MAX11645 Maxim Integrated Products, MAX11645 Datasheet - Page 10

• Manufacturer Part Number: MAX11645
• Description: 2-Wire Serial 12-Bit ADCs
• Manufacturer: Maxim Integrated Products

During the acquisition interval, the T/H switches are in
the track position and C
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on C
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
0V within the limits of a 12-bit resolution. This action
requires 12 conversion clock cycles and is equivalent
to transferring a charge of 11pF x (V
C
digital representation of the analog input signal.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of up to 1.5kΩ
does not significantly degrade sampling accuracy. To
minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog input
to GND. This input capacitor forms an RC filter with the
source impedance limiting the analog-input bandwidth.
For larger source impedances, use a buffer amplifier to
maintain analog-input signal integrity and bandwidth.
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the eighth rising clock edge
of the address byte. See the Slave Address section.
The T/H circuitry enters hold mode on the falling clock
edge of the acknowledge bit of the address byte (the
ninth clock pulse). A conversion or a series of conver-
sions is then internally clocked and the MAX11644/
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
Figure 4. Equivalent Input Circuit
10
T/H
T/H
______________________________________________________________________________________
to the binary weighted capacitive DAC, forming a
as a stable sample of the input signal.
AIN0
AIN1
GND
T/H
charges to the analog input
ANALOG INPUT MUX
IN+
- V
IN-
) from
C
C
T/H
T/H
MAX11645 hold SCL low. With external clock mode, the
T/H circuitry enters track mode after a valid address on
the rising edge of the clock during the read (R/W = 1)
bit. Hold mode is then entered on the rising edge of the
second clock pulse during the shifting out of the first
byte of the result. The conversion is performed during
the next 12 clock cycles.
The time required for the T/H circuitry to acquire an
input signal is a function of the input sample capaci-
tance. If the analog-input source impedance is high,
the acquisition time constant lengthens and more time
must be allowed between conversions. The acquisition
time (t
to be acquired. It is calculated by:
where R
R
clock mode and t
The MAX11644/MAX11645 feature input-tracking cir-
cuitry with a 5MHz small-signal bandwidth. The 5MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using under sampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
IN
= 2.5kΩ, and C
ACQ
SOURCE
) is the minimum time needed for the signal
t
ACQ
V
DD
/2
≥ 95 (R
is the analog-input source impedance,
ACQ
REF
REF
IN
= 22pF. t
= 2/f
CAPACITIVE
DAC
CAPACITIVE
DAC
SOURCE
Analog Input Bandwidth
SCL
ACQ
for external clock mode.
+ R
MAX11644
MAX11645
is 1.5/f
IN
) x C
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SCL
IN
for internal