MAX11645 Maxim Integrated Products, MAX11645 Datasheet - Page 13

• Manufacturer Part Number: MAX11645
• Description: 2-Wire Serial 12-Bit ADCs
• Manufacturer: Maxim Integrated Products

A write cycle begins with the bus master issuing a
START condition followed by seven address bits
(Figure 7) and a write bit (R/W = 0). If the address byte
is successfully received, the MAX11644/MAX11645
(slave) issues an acknowledge. The master then writes
to the slave. The slave recognizes the received byte as
the set-up byte (Table 1) if the most significant bit
(MSB) is 1. If the MSB is 0, the slave recognizes that
byte as the configuration byte (Table 2). The master
Figure 9. Write Cycle
Table 1. Setup Byte Format
(MSB)
BIT 7
REG
BIT
7
6
5
4
3
2
1
0
Configuration/Setup Bytes (Write Cycle)
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
______________________________________________________________________________________
BIP/UNI
NAME
BIT 6
SEL2
SEL2
SEL1
SEL0
REG
CLK
RST
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
X
A) ONE-BYTE WRITE CYCLE
B) TWO-BYTE WRITE CYCLE
1
S
1
S
SLAVE ADDRESS
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
Three bits select the reference voltage (Table 6).
Default to 000 at power-up.
1 = bipolar, 0 = unipolar. Defaults to 0 at power-up (see the Unipolar/Bipolar section).
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t-care bit. This bit can be set to 1 or 0.
Register bit. 1 = setup byte, 0 = configuration byte (Table 2).
1 = external clock, 0 = internal clock. Defaults to 0 at power-up.
7
7
SETUP OR CONFIGURATION BYTE
SETUP OR CONFIGURATION BYTE
MSB DETERMINES WHETHER
BIT 5
MSB DETERMINES WHETHER
SEL1
W
W
1 1
1 1
A
A
CONFIGURATION BYTE
CONFIGURATION BYTE
SETUP OR
SETUP OR
BIT 4
SEL0
8
8
A
A
1
1
P OR Sr
can write either one or two bytes to the slave in any
order (setup byte, then configuration byte; configura-
tion byte, then setup byte; setup byte or configuration
byte only; Figure 9). If the slave receives a byte suc-
cessfully, it issues an acknowledge. The master ends
the write cycle by issuing a STOP condition or a repeat-
ed START condition. When operating in HS mode, a
STOP condition returns the bus into F/S mode (see the
HS Mode section).
CONFIGURATION BYTE
1
BIT 3
CLK
SETUP OR
DESCRIPTION
8
NUMBER OF BITS
A
1
BIP/UNI
BIT 2
P OR Sr
1
NUMBER OF BITS
BIT 1
RST
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(LSB)
BIT 0
X
13