MAX11645 Maxim Integrated Products, MAX11645 Datasheet - Page 15

• Manufacturer Part Number: MAX11645
• Description: 2-Wire Serial 12-Bit ADCs
• Manufacturer: Maxim Integrated Products

A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing a
START condition followed by seven address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX11644/MAX11645 (slave) issues an
acknowledge. The master then reads from the slave.
The result is transmitted in 2 bytes; first 4 bits of the first
byte are high, then MSB through LSB are consecutively
clocked out. After the master has received the byte(s), it
can issue an acknowledge if it wants to continue read-
ing or a not-acknowledge if it no longer wishes to read.
If the MAX11644/MAX11645 receive a not-acknowl-
edge, they release SDA, allowing the master to generate
a STOP or a repeated START condition. See the Clock
Modes and Scan Mode sections for detailed information
on how data is obtained and converted.
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the set-
up byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX11644/MAX11645 are defaulted
to internal clock mode (CLK = 0).
When configured for internal clock mode (CLK = 0), the
MAX11644/MAX11645 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX11644/MAX11645 begin tracking the analog input
after a valid address on the eighth rising edge of the
Figure 10. Internal Clock Mode Read Cycles
A) SINGLE CONVERSION WITH INTERNAL CLOCK
B) SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
S
1
S
SLAVE ADDRESS
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
7
t
ACQ
7
t
ACQ1
1 1
R
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
A
1 1
R
A
CLOCK STRETCH
______________________________________________________________________________________
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
t
CONV
t
CONV1
CLOCK STRETCH
RESULT 4 MSBs
Data Byte (Read Cycle)
t
ACQ2
t
CONV2
8
A
Internal Clock
Clock Modes
CLOCK STRETCH
RESULT 8 LSBs
t
t
ACQN
CONVN
8
RESULT 1 ( 4MSBs)
1
A
P OR Sr
8
1
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While
converting the analog input signal, the MAX11644/
MAX11645 hold SCL low (clock stretching). After the
conversion completes, the results are stored in internal
memory. If the scan mode is set for multiple conver-
sions, they all happen in succession with each addi-
tional result stored in memory. The MAX11644/
MAX11645 contain two 12-bit blocks of memory. Once
all conversions are complete, the MAX11644/
MAX11645 release SCL, allowing it to be pulled high.
The master can now clock the results out of the memo-
ry in the same order the scan conversion has been
done at a clock rate of up to 1.7MHz. SCL is stretched
for a maximum of 8.3µs per channel (see Figure 10).
The device memory contains all of the conversion
results when the MAX11644/MAX11645 release SCL.
The converted results are read back in a first-in-first-out
(FIFO) sequence. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and points to the
first result. Note that only the current conversion results
are read from memory. The device must be addressed
with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
1
A
NUMBER OF BITS
RESULT 1 (8 LSBs) A
8
1
RESULT N (4MSBs)
8
1
A
RESULT N (8LSBs)
8
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1
A
P OR Sr
1
NUMBER OF BITS
15