MAX11645 Maxim Integrated Products, MAX11645 Datasheet - Page 5

• Manufacturer Part Number: MAX11645
• Description: 2-Wire Serial 12-Bit ADCs
• Manufacturer: Maxim Integrated Products

TIMING CHARACTERISTICS (Figure 1) (continued)
(V
1.7MHz, T
Note 1: For DC accuracy, the MAX11644 is tested at V DD = 5V and the MAX11645 is tested at V DD = 3V with an external
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to V
Note 7: When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µV
Note 9: Measured for the MAX11645 as:
Note 10: A master device must provide a data hold time for SDA (referred to V
Note 11: The minimum value is specified at T
Note 12: C
Note 13: f
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
DD
= 2.7V to 3.6V (MAX11645), V
reference for both ADCs. All devices are configured for unipolar, single-ended inputs.
offsets have been calibrated.
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit ).
and for the MAX11644, where N is the number of bits:
falling edge (see Figure 1).
A
SCL
PARAMETER
B
= T
⎡
⎢
⎢
⎣
⎡
⎢
⎢
⎣
= total capacitance of one bus line in pF.
⎡ ⎣
⎡ ⎣
V
must meet the minimum clock low time plus the rise/fall times.
V
MIN
FS
FS
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
( .
( .
3 6
to T
5 5
_______________________________________________________________________________________
V
V
( .
MAX
1-/2-Channel, 2-Wire Serial, 12-Bit ADCs
( .
3 6
)
5 5
)
−
−
V
, unless otherwise noted. Typical values are at T
V
V
V
FS
FS
−
−
2 7
4 5
( .
( .
2 7
.
4 5
.
V
V
V
)
V
DD
)
)
)
SYMBOL
⎤ ⎦ ×
⎤ ⎦ ×
t
SU
t
= 4.5V to 5.5V (MAX11644), V
t
RCL1
t
t
RDA
V
FDA
t
FCL
C
V
,
SP
2
REF
2
REF
B
STO
N
N
A
⎤
⎥
⎥
⎦
⎤
⎥
⎥
⎦
= +25°C.
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
(Notes 10 and 13)
CONDITIONS
DD
DD
DD
DD
REF
- 0.7V
- 0.7V
- 0.7V
- 0.7V
= 2.048V (MAX11645), V
A
= +25°C, see Tables 1–5 for programming notation.)
DD
DD
DD
DD
IL
(Note 11)
P-P
of SCL) to bridge the undefined region of SCL’s
.
DD
.
MIN
160
REF
20
20
20
20
0
= 4.096V (MAX11644), f
TYP
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MAX
160
160
160
400
80
10
UNITS
SCL
pF
ns
ns
ns
ns
ns
ns
5
=